6. Hardware Structure and System Signals
39
Milliwatt Computer System Modules or with a user-
designed module, as needed. Access holesforthecable
connections are provided in the chassis base. In
addition, rubber feet are provided, as well as holes for
vertical mounting.
The
CDP18S023 Power Converter
is a convenient,
compact power supply that plugs into any standard
110-volt 60-Hz wall outlet. It has a regulated output of
+5 volts dc ±5% at 600 milliamperes
The CDP18S023 can operate the 20 milliampere
loop interface and 5-volt ROM’s such as the CDP1834,
the 2758, or the 2716. Provision is made for the
addition of two auxiliary voltages. Backplane pins 11
and 20 are for a negative and a positive voltage,
respectively. For example, +12 volts and -5 volts on
these terminals allow the use of 2708 EPROM ’s as well
as the RS232C interface. The provision of +15 volts
and -15 volts would allow the use of analog circuits as
well as the RS232C interface.
System Signals
The C D P 18S693 and C D P 18S694 make use of the
following conventions for designating the system
signals. The designation for each signal may be
followed by a hyphen and either the letter N or the
letter P. The suffix N means that the signal is asserted
(true) when the wire is at ground. The suffix P means
that the signal is asserted (true) when that wire is at the
highest logic level (+5 V). Thus, the signal name gives
the meaning assigned to a specific conductor, and the
suffix defines the electrical value of the asserted (true)
state. An alternative convention uses a barred signal
(e.g. EF1) to indicate that the signal is asserted (true)
when the wire is at ground.
The signals on the universal backplane and theirpin
assignments are listed in Table IX. The majority of these
signals is derived from the CDP1802 Microprocessor;
the signals are described below. For additional
inform ation, refer to the
User Manual for the
CDP1802 Microprocessor,
MPM-201 and to the data
sheet for the CDP1802, File No. 1023.
TPA, TPB
—Timing pulses generated by the CPU
which occur once in each machine cycle. TPA trailing
edge is used to latch the high-order memory address.
TPB trailing edge is used to latch output data from the
data bus.
DB7
through
DBO—Eight bidirectional data bus
lines. Taken directly from the CPU bus pins, these lines
transfer data among the memory, CPU, and I/O
devices.
A7 through A0
—Eight memory address lines from
the CPU. The 16 memory address bits are multiplexed
on this address bus. The high-order eight bits are
presented early in each machine cycle and must be
latched at the TPA trailing edge. The CDP18S601
buffers, latches, and decodes these bits for the onboard
memories. Any external memory must provide its own
latches. During the latter part of the cycle, the low-
order eight bits are presented on this address bus and
need not be latched.
MWR
—A WRITE command from the CPU to the
memories. Address lines are stable at this time. Actual
writing or latching occurs at the trailing edge.
MRD
—A READ command from the CPU to the
memories and a direction indicator for I/O data
transfers. In the I/O instructions it corresponds to N3
(N register, internal to the CPU) which distinguishes
I/O inputs from outputs. MRD must be used to
condition output drivers in all memory components,
or their output buffers, to avoid contention on the data
bus. The absence of MWR must not be interpreted as a
READ. Early in a write cycle, data are being driven
onto the data bus by the CPU or an input device. If a
memory allows its outputs to be enabled while MRD is
false before MWR appears, bus contention will occur
resulting in unnecessary power dissipation and
perhaps circuit failures. O peration using the
Micromonitor CDP18S030 is impossible unless MRD
is properly used to condition data output.
Q
—A single-bit output from the CPU. This bit is set
or reset by SEQ (7B) or REQ (7A) instructions. The
CDP18S601 may use Q as a serial data output to the
RS232C and 20-mA data terminal drivers. It is also
available for other uses through the Microboard Bus
(P1) and Parallel I/O (P2) connectors. Q mayalso be
tested with a branch instruction and thereby operates
as a program switch.
N0, N1, N2
—taken directly from the CPU pins’
these lines indicate an I/O instruction is being
executed. They are derived from the low-order three
bits of the N register during an I/O instruction
execution only. They are low (false) at all other times.
These bits form the primary address identifying the
I/O device. Direction of transfer, derived from N3
internal to the C PU, is presented on the MRD line.
When high, MRD indicates data transfer from I/O to
memory; when low, from memory, to I/O.
EF1, EF2, EF3, EF4
—Taken directly to the CPU
pins, these inputs can be tested by conditional branch
instructions. The CDP18S601 uses EF1 and EF2,
conditioned by the secondary I/O address, to test the
READY state of I/O po rts A and B. The CDP18S652
uses conditioned EF1 to read serial data from the
cassette tape interface. The serial data interface input is
presented directly on EF4 or EF3 chosen by link LK36.
I/O devices using the INT line may make use of the EF
lines to identify the device. They may also be used to
indicate priority or status.
INT
—Taken directly to the CPU pin, the interrupt
line causes a transfer of control from the current
program counter to register 1. Interrupts may be
inhibited by software. If Interrupt Enable (IE) is set,
recognition of INT results in completion of execution
of the current instruction, followed by an S3 machine
state during which designators X and P are stored in T.
Then, X is set to 2, P is set to 1, and IE is reset to 0. The
S3 state lasts one machine cycle (eight clocks), after
which processing resumes with R1 as program
cou n t e r . ______
DMAI, DMAO
—Taken directly to the CPU pins
and not utilized by the CDP18S601, these lines allow
offboard I/O controllers rapid direct memory access.
