User Manual for Microboard Computer Development System CDP18S693 & CDP18S694
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EPROM ’s may be used in these sockets. Each of these
memory types may be placed independently in any of
the 16 four-kilobyte blocks comprisingthe64-kilobyte
system memory space.
With the CMOS programmable I/O Interface
CDP1851, the CDP18S601 provides the Prototyping
System with 20 programmable I/ O lines. The software
customizes each of these lines as input, output,
bidirectional, or bit-programmable with or without
unique handshaking signals for each application. A
serial communications interface, with both 20-
milliampere loop and EIA RS232C capability, is
driven by the Q and EF4 serial I/O lines of the CPU.
The baud rate and the data format are determined by
software. Edge connectors support the parallel I/O
lines and the Microboard Universal Backplane. Right-
angle header connections are used with the serial
communications interfaces.
The
CDP18S652 Combination Memory and Tape
I/O Control Module
contains sockets for 24 kilobytes
of ROM addressed in the upper half of memory. Also
on board is a 1 kilobyte block of RAM addressed in the
memory space 8C00H through 8FFFH. Two tape I/O
channels interface to audio cassette tape drives and
have software-controlled START/STOP throughthe
“REMOTE” jack. LED’s indicate I/O data flow for
each channel. A RESET/RUN switch connects to on
board CPU control logic to enable system startup at
8000H (UT62) or 0000H (user memory).
As shipped with the CDP18S693 System, the
CDP18S652 Module is augmented to contain the
UT62 monitor in ROM and BASIC3 in ROM. With
the CDP18S694 System, the Module also contains a
text editor and Level I assembler in ROM. Two
additional locations are available for two 2-kilobyte or
one 4-kilobyte EPROM or ROM.
For more detailed information about the CDP-
18S601 or CDP18S652 Microboard Modules, refer to
the MB-601 and Appendix G.
The ROM-based Utility Program UT62 operates
through any standard data terminal (EIA RS232C or
20-milliampere loop) to allow the user to monitor and
alter the contents of memory and to start execution at
any address. Operating details for the UT62 are given
in Chapter 2.
The
chassis
provided with the CDP18S693
development System can accommodate six Micro
board modules in addition to the CDP18S601 and
CDP18S652 supplied with the System. Because the
chassis utilizes the RCA COSMAC M icroboard
Universal Backplane (See Table IX for the Backplane
Connector Pin List), the Development System can
be readily expanded with any of the Microboard
Table IX— Pin Terminals and Signals
for the RCA COSMAC Universal Backplane Connector
Wire Side
Component Side
Signal
Signal
Pin Mnemonic
Flow
Description
Pin
Mnemonic
Flow
Description
A
T P A - P
O u t
S y s te m T im in g P u ls e 1
1
D M A I - N
In
D M A I n p u t R e q u e s t
B
T B P - P
O u t
S y s te m T im in g P u ls e 2
2
D M A O - N
In
D M A O u t p u t
C
D B 0 - P
l n / O u t
D a ta B u s
3
R N U - P
—
R u n U t i li t y R e q u e s t
D
D B 1 - P
l n / O u t
D a ta B u s
4
IN T - N
In
I n t e r r u p t R e q u e s t
E
D B 2 - P
l n / O u t
D a ta B u s
5
M R D - N
O u t M e m o r y R e a d
F
D B 3 - P
l n / O u t
D a ta B u s
6
Q - P
O u t
P r o g r a m m e d O u t p u t L a tc h
H
D B 4 - P
l n / O u t
D a ta B u s
7
S C 0 - P
O u t S ta te C o d e
J
D B 5 - P
l n / O u t
D a ta B u s
8
S C 1 - P
O u t S ta te C o d e
K
D B 6 - P
l n / O u t
D a ta B u s
9
C L E A R - N
In
C le a r - M o d e R e q u e s t
L
D B 7 - P
l n / O u t
D a ta B u s
10
W A I T - N
In
W a it - M o d e R e q u e s t
M
A 0 - P
O u t
M u lt ip le x e d A d d r e s s B u s
11
- 5 V / - 1 5 V
—
A u x il ia r y P o w e r
N
A 1 - P
O u t
M u lt ip le x e d A d d r e s s B u s
12
S P A R E
—
N o t A s s ig n e d
P
A 2 - P
O u t
M u lt ip le x e d A d d r e s s B u s
13
C L O C K O U T
O u t C lo c k f r o m C P U O s c .
R
A 3 - P
O u t
M u lt ip le x e d A d d r e s s B u s
14
N 0 - P
O u t
I/ O P r im a r y A d d r e s s
S
A 4 - P
O u t
M u lt ip le x e d A d d r e s s B u s
15
N 1 - P
O u t
I / O P r im a r y A d d r e s s
T
A 5 - P
O u t
M u lt ip le x e d A d d r e s s B u s
16
N 2 - P
O u t
I / O P r im a r y A d d r e s s
U
A 6 - P
O u t
M u lt ip le x e d A d d r e s s B u s
17
E F 1 - N
In
E x te r n a l F la g
V
A 7 - P
O u t
M u lt ip le x e d A d d r e s s B u s
18
E F 2 - N
In
E x te r n a l F la g
W
M W R - N
O u t
M e m o r y W r it e P u ls e
19
E F 3 - N
In
E x te r n a l F la g
X
E F 4 - N
In
E x te r n a l F la g
2 0
+ 1 2 V /+ 1 5 V
—
A u x il ia r y P o w e r
Y
+ 5 V
In
+5 v o lt s d c
21
+ 5 V
In
+5 v o lt s d c
Z
G N D
In
D ig it a l G r o u n d
2 2
G N D
In
D ig it a l G r o u n d
