AC 23 BLOCK DIAGRAM
CH.ln�
INPUT
�
L_
Rfl
CH. 1 LEVEL
(Off to +6d8)
CH. 2 LEVEL
(Off to +6d8)
CH. 2
FIL l£R
INPUT
I
I
FREQUENCY
I
I
(70Hz-1kHz)
L ___________
L __
J
NOT(: ALL $"'1TCHES SHO\\N "'1lH PLUCS NOT lNSERTEO
fREOUENCY
(450-71<Hz)
fREO\JENCY
(450-71<Hz)
DELAY
LF LEVEL
(0-2ms) (Off to +6<f8)
OELA Y
lF LEVEL
(0-2ms) (Off to +6<F.l)
HF LE\ltl
(Off to +6<f8)
3-PIN BALANCED
RANE l/4
K
IN (BAU
See Rane Note 11 O for other configurations.
� n�o�1\
'i.7J
(M4W: SUB OVT)
(nc)
(M5W: sue OVT)
DIAGRAM 11-1.
Wiring connections for balanced input or floating output operation.
15
Содержание AC 22
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