Hardware Reference Manual
421 Intelligent Serial, 8-Port
2 Theory of Operation
Handling serial I/O data generally imposes a high overhead on a processor. Data is converted to/ from a serial bit
stream by a UART device, which is character-based, usually with none to low amounts of internal data storage.
As a result, there is a distinct time constraint on the host to feed the UART. Failure to unload data will result in
data overrun (and lost information), not keeping the output filled reduces total data rate.
Modern processors and I/O bus protocols (e.g., PCI) are particularly unsuited for character style I/ O. Processor
performance is predicated on maintaining a continuous pipeline of data and instructions; interactions with external
I/O devices break the smooth flow of processing. I/O buses (such as PCI) extend this design in their realm,
depending upon longer burst (i.e., multiple cycle) transactions to mitigate protocol overheats. Single cycle (e.g.,
one to four byte) transactions on the PCI will be an order of magnitude less effective than burst transactions.
Each I/O device that requires fine grain control decreases the overall system performance by consuming an
excessive proportion of total resources.
While there are some UART devices with DMA capabilities, these are of limited use; setup overhead reduces
effectivity for small transfer sizes. In addition, serial data streams frequently include low-level protocols that
demand per-character response. (A simple example is software flow control.)
Inserting a processor into the design results in several benefits:
•
Decoupling connection to UART and host
•
Flexible engine to multiplex/demultiplex application buffers to/from UARTs
•
Dedicated resource to handle UART control to keep all channels operating at full line speeds
•
Provision to augment firmware with special protocol handling (e.g., encryption) with minimum effort. (All
firmware is in high-level language.)
The PMC421 takes advantage of the most recent technology in UART implementation, which allows deeper
hardware buffers and control to further augment overall data flow.
Refer to the block diagram for the design of the PMC421.
DDC No. Rx-URMH 002 Rev -
Issued 12 November 2002
7 of 19
