Hardware Reference Manual
421 Intelligent Serial, 8-Port
signaling characteristics are software controlled on a per-port-basis. The baud rate of each serial port is also
separately programmable: supported rates are from 150bps to 1.5Mbps.
Each port may use simple 3wire connection (TX/RX/GND) or full modem control. Hardware (RTS/CTS), Software
(Xon/Xoff) or no flow control is also set per-port via software. The PMC421 can be viewed as four functional
components:
1.1.2 PCI Interface
The PMC421 PCI interface is Revision 2.1 compatible, supporting 33MHz/32bit transactions. Both slave and
master operation are available, the latter including DMA engines capable of long PCI bursts. As data is buffered
in local DRAM, large blocking factors can be used (when application level protocols allow). Both programmed I/O
and message-based control is supported. The messaging system follows I2O hardware specifications.
1.1.3 Processor Resources
The on board 32 bit RISC CPU (i960VH) provides an external bus rate of 33MHz and an internal processor clock
rate of 100MHz. The higher CPU clock rate ensures sufficient bandwidth for all protocols (e.g. encryption) and
character manipulation at high, multi-port data rates. Local DRAM (4 Mbytes) is used for firmware execution and
character data buffering. Firmware is loaded automatically on power-up from local FLASH memory. New
firmware (e.g., upgrades) may be loaded in the field without removing the PMC421 from the host. The processor
directly controls both the UARTs and the Signal Drivers for full software configuration.
1.1.4 Programming Interface
Flexibility, efficiency and use with both new and existing applications were all considered during the design of the
Application Interface. Several modes of data transfer are supported, including a traditional programmed I/O (i.e.,
pseudo register) and high performance messaging. The "pseudo register" interface allows a host to use
programmed I/O cycles to set characteristics and transmit/receive data. While less efficient, this mode can be
appropriate for simple (low-speed) operation as well as when adapting legacy code. The messaging interface
allows simple, efficient transfers between host software and the PMC421. A control block contains transaction-
specific information such as configuration, data or location of data buffers. A message queuing system makes
transfer of the control blocks between the host and PMC421 very simple with minimal software development.
Once submitted to the PMC421, the transaction information is loaded by the local processor; for large data
blocks, the DMA engines are utilized to execute the data movement. This improves PCI bus utilization as well as
allowing scatter/gather operation (useful in virtual memory operating systems).
1.1.5 Serial Ports
Each serial data stream is controlled with a UART, which is responsible for Serialization/De-Serialization and, if
enabled, hardware flow control. Each serial port has independent configuration parameters for speed and flow
control, etc. Intrinsic to each UART is a deep FIFO buffer to prevent data loss under high or bursty loads. The
UART can also control software flow control, ensuring very rapid response to the incoming data stream.
1.1.6 Line Drivers
In traditional Serial Interface cards, the various electrical signaling protocols (e.g., RS232, RS422) were
configured via switches or jumpers. This increases the potential for difficult-to-detect-errors. On the PMC421,
DDC No. Rx-URMH 002 Rev -
Issued 12 November 2002
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