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Chapter 4: Theory of operation
57
General purpose I/Os
The T8105 includes these General Purpose (GP) I/Os:
1
For more information, see ECTF H.110 spec. RV1.0, section 4.3.2.
2
For more information, see ECTF H.110 spec. RV1.0, section 4.4
Clocking
T8105 clocking is complex and beyond the scope of this guide. Only clock sources
are identified here; for an in-depth overview of clocking the T8105, reference
the T8105.
GP
I/O
Signal
Name
Default
Value
Function
Default
Function
0
T8105:PRIREFOUT_~OE
1
Enables the primary ref out
(P5) to 4MhzIN (U2).
Primary reference out is
isolated from 4MhzIN
1
Unused
1
–
–
2
CT:CLK_PRI
1
Shorts out the 33 ohm
termination resistor for
CT:C8_A, and
CT:~FRAMEA
Defaults to 33 ohm R’s in
the circuit. Bypass the 33
ohms if the card is the
H.110 bus master.
1
3
CT:CLK_SEC
1
Shorts out the 33 ohm
termination resistor for
CT:C8_B, and
CT:~FRAMEB
Defaults to 33 ohm R’s in
the circuit. Bypass the 33
ohms if the card is the
H.110 bus master.
1
4
CT:RESET
1
Allows Local PCI reset to
propagate to the H.110
CT:RESET.
Local PCI reset isolated
from H.110 Bus.
2
5
T8105:~KEEPSEL
1
Enables strong keepers on
T8105 H.110 bus signals
(Undocumented feature of
T8105)
Default is weak keepers.
Table 4-5. T8105 clock sources
Signal
Description
OSC
Local XTAL, 16.384MHz.
NETREF1
Clock to/from H.110 interface, provides network
synchronization to digital trunk.
NETREF2
Clock to/from H.110 interface, provides network
synchronization to digital trunk.
LREF[0:7]
Local reference, from PMC site.
H.110 A-Clocks
from H.110 interface, bit clock driven from the A
master, 8.192MHz.
H.110 B-Clocks
from H.110 interface, bit clock driven from the B
master, 8.192MHz.
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