Chapter 4: Theory of operation
47
Memory map
The 2
32
byte physical address space seen by the Pentium occupies these areas:
•
From 0 to 1 MB is largely defined by the IBM PC/AT architecture.
•
From 1 to 256 MB depends on the amount of installed DRAM.
•
Memory addresses from the Pentium between 0 and 4 MB (0FFFFFFFh) is
mapped as follows:
1
If no BIOS extensions, ISA bus (aliased); not cacheable.
2
If no DRAM, ISA bus (aliased); not cacheable.
Interrupt usage
For details about EPC-3307 PC-compatible interrupt usage, see
Appendix B,
Interrupts
.
Flash boot device
A Boot Block Flash memory stores system start-up code for the CPU board. This
flash-updatable BIOS contains the boot, main, and parameter blocks shown in
Figure 4-2
. The Main and Parameter blocks of the BIOS are reprogrammed under
program control. Registers contained within the 440GX protect these areas from
inadvertent writes. The BIOS chip select signal asserts only when the chipset is to
write within the range of the BIOS Flash boot device.
As a build-time option, the main board may have eight pages of Flash at the top of
memory. Each page is 512k bytes, in an 8-bit format. One of the pages, the PC BIOS
page, has a boot block architecture. The remaining seven pages are made from an
Intel Strata Flash. The BIOS control Register in the CPLD controls which page is
active. On initial power-up, the BIOS Control Register is set to point at the top of
the boot block flash, where the PC BIOS resides. At a later time, software can select
Range
Content
Cacheable
0–640Kb
00000000–0009FFFF
First 640 KB of DRAM
(DOS memory)
Yes
640Kb–1MB
000A0000–000BFFFF
VGA video DRAM, mapped to
the Video Module
No
000C0000–000CBFFF
Write-protected DRAM
containing shadowed video
BIOS (48 KB)
Yes
000D0000–000DFFFF
BIOS extensions
Yes
1
000E0000–000FFFFF
System BIOS shadow
Yes
1MB–512MB
00100000–0FFFFFFF
DRAM (511 MB)
Yes
2
512MB–
top 1MB
10000000–FFEFFFFF
ISA bus (aliased)
No
Top 1MB
FFF00000–FFFFFFFF
Flash memory
No
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