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EPC-3307 Hardware Reference
88
J2 connector
The CompactPCI J2 connector is exactly the same as the J1 connector except there
are only 22 rows numbered 1
–
22, and the center guide lug is eliminated. All these
signals have the standard CompactPCI revision 2.1 bus definitions.
Notes:
1
This diagram defines the pin assignments from the front of the system chassis. All
pins are medium length (level 2) except connector J1 pins C16 and D15, which
are long (level 3) and short (level 1), respectively.
2
The V(I/O) signals are either 5V or 3.3V, depending on the system
implementation.
3
The following positions in rows 1–3 of connector P2 are implemented on the
System Slot board: A1–3, B2, C1–3, and E1–3. Additionally, the following
positions in rows 15–17 and 19–21 of connector P2 are also implemented only on
the System Slot board: C15, C16, D17, E15, E17, A19, A21, B19, B20 and B21.
Table C-2. CompactPCI J2 connector
Pin
A
B
C
D
E
F
8
1
3
RSV
GND
RSV
RSV
RSV
GND
2
3
RSV
RSV
UNC
(4)
RSV
RSV
GND
3
3
RSV
GND
RSV
RSV
RSV
GND
4
V(I/O)
BRSV
C/~BE[7]
GND
C/~BE[6]
GND
5
C/~BE[5]
GND
V(I/O)
2
C/~BE[4]
PAR64
GND
6
AD[63]
AD[62]
AD[61]
GND
AD[60]
GND
7
AD[59]
GND
V(I/O)
2
AD[58]
AD[57]
GND
8
AD[56]
AD[55]
AD[54]
GND
AD[53]
GND
9
AD[52]
GND
V(I/O)
2
AD[51]
AD[50]
GND
10
AD[49]
AD[48]
AD[47]
GND
AD[46]
GND
11
AD[45]
GND
V(I/O)
2
AD[44]
AD[43]
GND
12
AD[42]
AD[41]
AD[40]
GND
AD[39]
GND
13
AD[38]
GND
V(I/O)
2
AD[37]
AD[36]
GND
14
AD[35]
AD[34]
AD[33]
GND
AD[32]
GND
15
BRSV
GND
RSV
RSV
RSV
GND
16
BRSV
BRSV
RSV
GND
BRSV
GND
17
BRSV
GND
RSV
RSV
RSV
GND
18
BRSV
BRSV
BRSV
GND
BRSV
GND
19
RSV
RSV
RSV
RSV
RSV
GND
20
RSV
RSV
RSV
GND
RSV
GND
21
RSV
RSV
RSV
RSV
RSV
GND
22
GA4
12
GA3
12
GA2
12
GA1
12
GA0
12
GND
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