EPC-3307 Hardware Reference
54
mapping requirements, Class Code, Subsystem ID and Subsystem Vendor ID, and
others. During the preload operation, all accesses to the 21554 configuration
registers receive a target retry.
CPU board reset on host command over CompactPCI
The CPU board may be reset independently of other system peripherals by the
System Slot CPU. This is achieved by having the Host write to the Reset Control
register in the Drawbridge’s PCI configuration space. The secondary reset out from
the Drawbridge forces a hard reset of the CPU board. The host can use bit-0 and
bit-1. To hold the CPU board in reset, the Host writes a value of one to D8. The
board then stays in reset until the Host clears that bit. To only reset the board, the
Host sets D8 to a value of two. This resets the board and self-clears, requiring no
further action by the Host.
Reset Control register
Primary byte offset: DB:D8h
Secondary byte offset: DB:D8h
Bit
Name
R/W
Description
0
Secondary reset
R/(WP)
Secondary bus reset. Possible values include:
0
(Disabled) The 21554 deasserts s_rst_l.
This bit must be cleared by a configuration
write in the case when it is set by a
configuration write. Otherwise, it clears
automatically after 100 msec or when
p_rst_l deasserts.
1
(Chip reset; R/(WP) ) The 21554 asserts
s_rst_l. This bit is set automatically when
the Chip Reset bit is written with a 1 or
when p_rst_l is asserted, or is set with
aconfiguration write.
1
Chip reset
R/(WP)
Chip reset control. Possible values include:
1 Causes the 21554 to perform a chip reset
and to assert s_rst_l.
Data buffers, configuration registers, and
both the primary and secondary interfaces
are reset to their initial state. The 21554
clears this bit once chip reset is complete.
0
(Disabled; reset value) The 21554
deasserts s_rst_l.
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