that the EPC-2 can access the global memory with the same addresses as used by
other processors without needing to understand that the memory is actually on-
board.
This ability is also useful in system checkout (i.e., checking operation of the
backplane) and in giving an EPC-2 program the ability to view its memory in
.i.big endian; format.
Read-Modify-Write Operations
.i.RMW cycle;Read-modify-write cycle;The EPC-2 provides synchronization
integrity in its local DRAM between accesses from the 386 into the DRAM and RMW
VXI accesses from other masters into the DRAM.
When a VXIbus slave read access occurs to the local DRAM, the EPC-2 watches the
VXIbus data and address strobes to determine if the cycle is an RMW cycle. If
it is, accesses by the 386 are held up until the terminating access of the RMW
cycle occurs.
When the 386 performs a locked access (e.g., via an instruction using the
.i.LOCK instruction prefix;) to the local DRAM, VXIbus read and RMW slave
accesses are held up until the last locked access completes.
.i.self accesses;One more case of interest is when the EPC-2 performs a locked
access that results in a self access. These function correctly (i.e., as if the
access were not a self access), providing that operating-system tables (e.g.,
.i.page tables;) that are accessed by the 386 by implicit locked accesses are
not mapped into VXI. This would only be a concern for user-written operating
systems.
VXIbus Interrupt Acknowledgement
When it asserts an interrupt, the EPC-2 formulates a .i.status/ID; value that is
transmitted on the bus as the response to a matching .i.interrupt
acknowledge;ment cycle. The EPC-2 acts as a D16 interrupter. The lower eight
bits of the status/ID value are the EPC-2's ULA, and the source for the upper
eight bits is specified by the IST bit in the .i.MSC; .i.module status/control
register;.
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