1257 User Manual
SCPI Command Basics 5-10
EADS North America Defense
Test and Services, Inc.
©
2001
This bit is set when a device-dependent error is detected. For
example, a channel in the 1257 drawer is read during power-up but
contains an unknown identification byte value. When this error
occurs, an error is added to the error message queue.
QYE
Query
Error
Bit 2, Bit weight = 4 decimal = 4 hexadecimal
This bit is set when a query error is detected. For
example, a query is sent, but the reply is not read,
and a second query or command is sent. When this
error occurs, an error is added to the error message
queue.
RQC
Request
Control
Bit 1, Bit weight = 2 decimal = 2 hexadecimal
This bit is never set by the 1257 and will always
read 0.
OPC
Operation
Complete
Bit 0, Bit weight = 1 decimal = 1 hexadecimal
This bit is set when the *OPC command is
executed. This may be used to synchronize the
1257 with the commands (to ensure that the 1257
command buffer is empty).
A bit is set in this register when the corresponding condition
becomes true. It remains set until the *ESR? query is executed.
When the query is executed, the reply contains the present value
of the register, and the register is then cleared to 0.
The value returned by the *ESR? query represents a sum of the
bit-weight values for all conditions that are true. For example, if the
PON bit is set and the QYE bit is set, and the rest of the bits are
cleared, then the value returned for the *ESR? query is:
PON + QYE = 128 + 4 = 132
The
Standard Event Status Enable Register
provides a mask
register. The value of this register is logically ANDed with the
Standard Event Status Registe
. If the value of this ANDing is
nonzero, then bit 5 of the
Status Byte Register
is set. This bit is
known as the “Event Summary Bit”, or ESB.
