1256 User Manual Publication No. 980855 Rev. A
SCPI Command Basics 5-22
EADS North America Test and Services
The
Operation Status Event Register
latches the status
information. Once a bit is set in the
Operation Status Event
Register
, it remains set until the bit is cleared by reading the
register with the STATUS:OPERATION:EVENT? query, or by
sending the *CLS command.
When any of the bits of the
Operation Status Event Register
are
set, bit 7 of the
Status Byte Register
will be set.
The
Questionable Status Register
is not used by the 1256. When
the
Questionable Status Condition Register
or
Questionable Status
Event Register
are read, they will return a value of 0. The
Questionable Status Event Register
may be programmed and
queried, but will have no effect on the operation of the 1256.
The following SCPI command tree shows the syntax of the SCPI
STATUS commands:
:STATus
:OPERation
[:EVENt]?
:CONDition?
:ENABle
:QUEStionable
[:EVENt]?
:CONDition?
:ENABle
Examples of the commands are shown below. To enable the “Wait
for Trigger” and “Wait for Arm” bits the following command
achieves this:
STAT:OPER:ENABLE
96
To read the value of the enable register:
STAT:OPER:ENABLE?
To read the value of the event register (and clear the event
register):
STAT:OPER?
To read the value of the condition register:
STAT:OPER:COND?
These commands augment the IEEE-488.2 Common Commands
to provide additional status information.
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