A– 6
RabbitCore RCM2200 Specifications
RabbitCore RCM2200
Figure A–3 shows a typical timing diagram for the Rabbit 2000 microprocessor external memory read and
write cycles.
T
adr
is the time required for the address output to reach 0.8 V. This time depends on the bus loading. T
setup
is
the data setup time relative to the clock. Tsetup is specified from 30%/70% of the V
DD
voltage level.
Figure A–3:
Memory Read and Write Cycles
Tadr
Tadr
External I/O Read (no extra wait states)
Thold
valid
CLK
A[15:0]
D[7:0]
valid
Tsetup
Thold
External I/O Write (no extra wait states)
CLK
A[15:0]
D[7:0]
/CSx
/OEx
/CSx
/WEx
valid
T1
Tw
T1
Tw
T2
valid
T2
valid
/IOCSx
/IORD
/BUFEN
valid
/IOCSx
/IOWR
/BUFEN
Содержание RCM2200
Страница 1: ...RabbitCore RCM2200 C Programmable Module with Ethernet User s Manual 019 0097 010418 A...
Страница 6: ...vi RabbitCore RCM2200...
Страница 10: ...1 4 Introduction RabbitCore RCM2200...
Страница 20: ...2 10 Hardware Reference RabbitCore RCM2200...
Страница 26: ...3 6 Software Reference RabbitCore RCM2200...
Страница 36: ...A 10 RabbitCore RCM2200 Specifications RabbitCore RCM2200...
Страница 42: ...C 4 Programming Cable RabbitCore RCM2200...
Страница 48: ...D 6 Sample Circuits RabbitCore RCM2200...
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Страница 52: ...E 4 External Interrupts RabbitCore RCM2200...
Страница 57: ...C NONE...
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