BL4S200 User’s Manual
189
The tables in this appendix are useful for both finding the cause of mode conflicts, and for
planning which pins to use for which functions to avoid conflicts in the first place. Note
that pins DIO30 and DIO31 do not have their output functionality controlled by a RIO
chip. This means that you cannot assign PWM or PPM functions to these two pins. On the
other hand, both of these pins have a counter block that is not shared with any other pins
on their inputs, which makes these pins ideal for use as counter or capture inputs.
Notice that there is a pattern to the block sharing of certain configurable I/O pins. The first
16 configurable I/O pins, DIO0—DIO15, have blocks shared across four inputs or four
outputs. These are the only pins that can support functions such as Quadrature Decoder
inputs with an independent index-based reset. The next group of 12 configurable I/O pins
(DIO16–DIO27) share blocks among their configurable I/O pairs, bringing both the input
and output functionality of these pins into the same block. This allows PWM or PPM out-
puts that can be used with an external synchronization signal. It would also allow synchro-
nization of a pulse capture response to a PWM-based output pulse. The last 4 configurable
I/O pins have nonshared RIO blocks available for both the input and output functionality,
making these pins ideal for single-pin functions requiring a counter/timer.
Table D-3 shows all counter/timer modes of the RIO block and which functions can use
the given modes. The use of synch signals is allowed with all the functions, but does affect
the timer/counter so it may have an adverse affect on functions marked with * or #.
× — I/O are compatible with the given mode, and can work with any other function
using that mode.
* — I/O cannot share the block with any other * or # marked function without
possible conflicts.
# — I/O can generally share the timer, but will be affected by settings of the limit
value (value at which the timer rolls over) or resetting of the counter, either
directly or through synch signals.
Table D-3. RIO Counter/Timer Block Mode Summary
Up Count
Count
Until
Match
Up/Down
Count
Free-
Running
Timer
Count
Until
End
Count
from
Begin to
End
Count
While
Begin Is
Active
Digital Input
×
×
×
×
×
×
×
Digital Output
×
×
×
×
×
×
×
Event Counter Input
*
*
*
Event Capture Input
#
*
*
*
Quad. Decoder Input
*
Ext. Interrupt Input
×
×
×
×
×
×
×
External Synch Input
×
×
×
×
×
×
×
PWM/PPM Output
#
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