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User’s Manual
109
10. I/O B
ANK
C
ONTROL
R
EGISTERS
The pins of Port E can be set individually to be I/O strobes. Each of the eight possible I/O
strobes has a control register that controls the nature of the strobe and the number of wait
states that will be inserted in the I/O bus cycle. Writes can also be suppressed for any of
the strobes. The types of strobes are shown in Figure 10-1. Each of the eight I/O strobes is
active for addresses occupying 1/8th of the 64K external I/O address space.
Figure 10-1. External I/O Bus Cycles
Table 10-1 shows how the eight I/O bank control registers are organized.
Table 10-1. I/O Bank Control Reg (adr IBxCR = 08xh)
Bits 7,6
*
* Total number of external I/O read/write wait states, including the one wait state
that is always present.
Bits 5,4
Bit 3
Bits 2–0
Wait state code
11-1
10-3
01-7
00-15
/IX strobe type
00—chip select
01—read strobe
10—write strobe
11—or of read and
write strobe
1—permit write
0—inhibit write
Ignored
ADDR
T1
Tw
T2
write data
write strobe
read data
read strobe
chip select strobe
valid
valid
valid
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