
QM1004-0.5-18 Combined RF Upconverter/Downconverter
User Manual
3. System Block Diagram
System block diagrams for the QM1004-0.5-18 Combined RF Upconverter/Downconverter are shown in
Figures 1.2 and 1.3. Internal attenuators in the upconverter and downconverter blocks are controlled
digitally via a microcontroller, which interfaces to a PC through USB or TCP/IP. The microcontroller out-
puts basic status messages on a 32-character Liquid Crystal Display (LCD) mounted on the faceplate
of the unit. An internal 10 MHz reference clock is phase-locked to all of the internal LOs, with a BNC-F
connector providing the option for LOs to lock to a user-provided 10 MHz external reference. An additional
BNC-F connector forwards the 10 MHz reference back out for use by external test equipment. Switching
between the internal and external LO reference clocks is controlled either by the microcontroller or a ref-
erence selector switch. The 21.5-39 GHz LO1 and 23.5 GHz LO2 outputs are provided for external phase
locking. A bypass switch also allows the inputs to bypass the converters and be output directly.
Figure 1.2:
QM1004–0.5–18 Upconverter Block Diagram
Figure 1.3:
QM1004–0.5–18 Downconverter Block Diagram
Quonset Microwave
Revision 1.2.1
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