Smart LTE Module Series
SC600Y&SC600T Hardware Design
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3.23.2. Reference Circuit Design for Earpiece Interface
EAR_P
EAR_N
R2
33pF
33pF
33pF
C2
C3
C1
R1
Module
D1
D2
0R
0R
Figure 29: Reference Circuit Design for Earpiece Interface
3.23.3. Reference Circuit Design for Headphone Interface
20K
ESD
MIC_GND
MIC2_P
HPH_L
HS_DET
HPH_R
HPH_REF
33pF
Module
R1
0R
3
6
4
5
2
1
33pF 33pF
C3
C4
C5
F3
F2
F1
D1 D2 D3 D4
F4
R2
R3
0R
Figure 30: Reference Circuit Design for Headphone Interface