Smart LTE Module Series
SC600Y&SC600T Hardware Design
SC600Y&SC600T_Hardware_Design 68 / 128
signal (negative)
DSI1_LN0_P
104
AO
LCD1 MIPI lane 0 data
signal (positive)
DSI1_LN1_N
107
AO
LCD1 MIPI lane 1 data
signal (negative)
DSI1_LN1_P
106
AO
LCD1 MIPI lane 1 data
signal (positive)
DSI1_LN2_N
109
AO
LCD1 MIPI lane 2 data
signal (negative)
DSI1_LN2_P
108
AO
LCD1 MIPI lane 2 data
signal (positive)
DSI1_LN3_N
111
AO
LCD1 MIPI lane 3 data
signal (negative)
DSI1_LN3_P
110
AO
LCD1 MIPI lane 3 data
signal (positive)
The following are the reference designs for LCM interfaces.
DSI0_CLK_P
LEDA
NC
LEDK
LPTE
NC (SDA-TP)
VIO18
NC (VTP-TP)
DSI0_LN3_P
LCD0_TE
LCD0_RST
DSI0_LN3_N
DSI0_LN2_P
DSI0_CLK_N
DSI0_LN2_N
RESET
LCD_ID
NC (SCL-TP)
NC (RST-TP)
NC (EINT-TP)
GND
VCC28
GND
MIPI_TDP3
MIPI_TDN3
GND
MIPI_TDP2
MIPI_TDN2
GND
MIPI_TDP1
MIPI_TDN1
GND
LDO17_2P85
LDO 6_1P8
LCD_BL_A
LCD_BL_K1
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
MIPI_TDP0
MIPI_TDN0
GND
MIPI_TCP
MIPI_TCN
29
28
30
3
4
5
6
3
4
5
6
3
4
5
6
3
4
5
6
DSI0_LN1_N
DSI0_LN1_P
DSI0_LN0_N
DSI0_LN0_P
1
2
3
4
5
6
11
1
2
1
2
1
2
1
2
100nF
4.7uF
1uF
Module
LCM
FL1
FL2
FL3
FL4
FL5
EMI filter
C3
C2
C1
NC
GND
GND
GND
GND
PMI_ MPP1
31
32
33
34
LCD_BL_K2
Figure 20: Reference Circuit Design for LCM0 Interface