Quectel FCM561D-P, Проектирование аппаратного обеспечения

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Wi-Fi&Bluetooth Module Series
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Table 10: Pin Definition of SDIO Interface
The following figure shows the SDIO interface connection between the module and the host:
SDIO_CLK
SDIO_CMD
SDIO_DATA0
SDIO_DATA1
SDIO_DATA2
SDIO_DATA3
Host Module
SDIO_DATA0
SDIO_DATA1
SDIO_DATA2
SDIO_DATA3
SDIO_CLK
SDIO_CMD
N
M
VBAT
N
M
N
M
N
M
N
M
N
M
N
M
NM
NM NM NM
NM
Figure 5: SDIO Interface Connection
To ensure compliance of interface design with the SDIO 2.0 specification, it is recommended to adopt
the following principles:
⚫
Route the SDIO traces in inner layer of the PCB, and surround the traces with ground on that layer
and with gr
ound planes above and below. The impedance of SDIO signal trace is 50 Ω ±10 %.
⚫
Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits and analog
Pin Name Pin No. Multiplexing Function I/O Description Comment
GPIO2 21 SDIO_CLK DIO SDIO clock
Other SDIO
configurations,
see Table 6 .
GPIO3 20 SDIO_CMD DIO SDIO command
GPIO4 19 SDIO_DATA0 DIO SDIO data bit 0
GPIO5 18 SDIO_DATA1 DIO SDIO data bit 1
GPIO10 37 SDIO_DATA2 DIO SDIO data bit 2
GPIO11 38 SDIO_DATA3 DIO SDIO data bit 3