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LTE-A Module Series

EG060V-EA Hardware Design

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This floor life is only applicable when the environment conforms to

IPC/JEDEC J-STD-033

2. To avoid blistering, layer separation and other soldering issues, it is forbidden to expose the modules

to the air for a long time. If the temperature and moisture do not conform to

IPC/JEDEC J-STD-033

the relative moisture is over 60 %, It is recommended to start the solder reflow process within 24

hours after the package is removed. And do not remove the packages of tremendous modules if they

are not ready for soldering.

3. Please take the module out of the packaging and put it on high-temperature resistant fixtures before

the baking. If shorter baking time is desired, please refer to

IPC/JEDEC J-STD-033

for baking

procedure.

7.2. Manufacturing and Soldering

Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the

stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly

so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the

thickness of stencil for the module is recommended to be 0.15

–0.18 mm. For more details, please refer to

document [2]

It is suggested that the peak reflow temperature is 238

–246 ºC, and the absolute maximum reflow

temperature is 246 ºC. To avoid damage to the module caused by repeated heating, it is strongly

recommended that the module should be mounted after reflow soldering for the other side of PCB has

been completed. The recommended reflow soldering thermal profile (lead-free reflow soldering) and

related parameters are shown below.

NOTES

Содержание EG060V-EA

Страница 1: ...EG060V EA Hardware Design LTE A Module Series Version 1 0 Date 2020 09 15 Status Released www quectel com ...

Страница 2: ...or notice Disclaimer While Quectel has made efforts to ensure that the functions and features under development are free from errors it is possible that these functions and features could contain errors inaccuracies and omissions Unless otherwise provided by valid agreement Quectel makes no warranties of any kind implied or express with respect to the use of features and functions under developmen...

Страница 3: ...eless Solutions Co Ltd Transmitting reproducing disseminating and editing this document as well as using the content without permission are forbidden Offenders will be held liable for payment of damages All rights are reserved in the event of a patent grant or registration of a utility model or design Copyright Quectel Wireless Solutions Co Ltd 2020 All rights reserved ...

Страница 4: ...LTE A Module Series EG060V EA Hardware Design EG060V EA_Hardware_Design 3 82 About the Document Revision History Version Date Author Description 1 0 2020 09 15 King MA Benjamin CHAI Initial ...

Страница 5: ...p Mode via USB with Suspend Resume and Remote Wakeup 28 3 5 1 3 Set Sleep Mode via USB with Suspend Resume and RI Function 29 3 5 1 4 Set Sleep Mode via USB without USB Suspend Function 30 3 5 2 Airplane Mode 30 3 6 Power Supply 31 3 6 1 Power Supply Pins 31 3 6 2 Decrease Voltage Drop 32 3 6 3 Reference Design of Power Supply 33 3 6 4 Monitor Power Supply 34 3 7 Turn on off 34 3 7 1 Turn on the M...

Страница 6: ...9 4 2 Antenna Installation 61 4 2 1 Antenna Requirement 61 4 2 2 Recommended RF Connector for Antenna Installation 61 5 Electrical Reliability and Radio Characteristics 63 5 1 Absolute Maximum Ratings 63 5 2 Power Supply Ratings 64 5 3 Operation and Storage Temperatures 64 5 4 Current Consumption 65 5 5 RF Output Power 67 5 6 RF Receiving Sensitivity 68 5 7 Electrostatic Discharge 68 5 8 Thermal C...

Страница 7: ...inition of Network Mode Status Indication Pins 47 Table 18 Working State of Network Mode Status Indication Pins 48 Table 19 Pin Definition of STATUS 49 Table 20 Behavior of RI 50 Table 21 Pin Definition of PCIe Interface 50 Table 22 Pin Definition of WLAN Control Interface 51 Table 23 Pin Definition of SD Card Interface 52 Table 24 Pin Definition of SPI Interface 54 Table 25 Parameters of SPI Inte...

Страница 8: ... USB Interface 41 Figure 21 Reference Design of Translator Chip 43 Figure 22 Reference Design of Transistor Circuit 44 Figure 23 Primary Mode Timing 45 Figure 24 Reference Design of PCM Interface with Audio Codec 46 Figure 25 Reference Design of Network Indicator 48 Figure 26 Reference Design of STATUS 49 Figure 27 Reference Design of SD Card Interface 53 Figure 28 SPI Interface Timing 54 Figure 2...

Страница 9: ...Bottom Dimensions Bottom View of the Module 73 Figure 43 Recommended Footprint Top View 74 Figure 44 Top View of the Module 75 Figure 45 Bottom View of the Module 75 Figure 46 Recommended Reflow Soldering Thermal Profile 78 Figure 47 Tape Specifications 79 Figure 48 Reel Specifications 79 ...

Страница 10: ...miliarizes you with the module s interface specifications electrical and mechanical details as well as other related information To facilitate application of the module in different fields its reference designs are also provided for your reference With this hardware design document along with the application notes and user guides explicated therein you can use the product to design and set up mobi...

Страница 11: ...devices may cause interference on sensitive medical equipment so please be aware of the restrictions on the use of wireless devices when in hospitals clinics or other healthcare facilities Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions such as when the mobile bill is unpaid or the U SIM card is invalid When emerg...

Страница 12: ...nuous intra band CA but not non continuous intra band CA With a compact profile of 37 0 mm 39 5 mm 3 05 mm EG060V EA can meet almost all requirements for M2M applications such as automotive applications meters tracking systems security systems routers wireless POS systems mobile computing devices PDA phones tablet PCs etc EG060V EA is an SMD type module which can be embedded into applications thro...

Страница 13: ...irection FDD Max 300 Mbps DL 50 Mbps UL TDD Max 220 Mbps DL 30 Mbps UL UMTS Features Support 3GPP R7 HSPA HSDPA HSUPA and WCDMA Support QPSK 16QAM and 64QAM modulation HSDPA Max 21 Mbps DL 2 HSUPA Max 5 76 Mbps UL WCDMA Max 384 kbps DL 384 kbps UL Internet Protocol Features Support PPP TCP UDP FTP HTTP NTP PING HTTPS SMTP MMS FTPS SMTPS SSL protocols Support PAP and CHAP for PPP connections SMS Te...

Страница 14: ...ion data transmission firmware upgrade software debugging Support USB serial drivers for Windows 7 8 8 1 10 WinCE 5 0 6 0 7 0 Linux 2 6 3 x 4 1 4 14 Android 4 x 5 x 6 x 7 x 8 x UART Interfaces Main UART Used for AT command communication and data transmission Baud rate reaches up to 921600 bps 115200 bps by default Support RTS and CTS hardware flow control Debug UART Used for Linux console and log ...

Страница 15: ...e functional diagram of EG060V EA with its major functional parts illustrated Power management Baseband LPDDR SDRAM NAND flash memory Radio frequency Peripheral interfaces Baseband PMIC Transceiver NAND DDR2 SDRAM Tx Rx Blocks ANT_MAIN ANT_DIV VBAT_BB VBAT_RF APT PWRKEY ADCs VDD_EXT USB 2 0 U SIM PCM UARTs I2C RESET_N 32 768 kHz GPIOs Control IQ Control Tx PRx DRx PCIe SD 26 M TCXO SPI Figure 1 Fu...

Страница 16: ...EG060V EA_Hardware_Design 15 82 2 4 Evaluation Board To help you develop applications handily with EG060V EA Quectel supplies an evaluation board EVB USB to RS 232 converter cable earphone antenna and other peripherals to control or test the module ...

Страница 17: ...d to a cellular application platform The following chapters describe the interfaces listed below Power supply U SIM interface USB interface UART interfaces PCM and I2C interfaces ADC interfaces Network indication Interfaces Module status indication Interface RI behaviors PCIe interface WLAN control interface SD card interface SPI interface USB_BOOT interface means under development NOTE ...

Страница 18: ... 56 MAIN_CTS 58 MAIN_RXD 60 MAIN_TXD 62 MAIN_DTR 64 GND 66 PCM_DIN 68 PCM_DOUT 70 GND 72 RESERVED 74 RESERVED 76 GND 78 RESERVED 80 RESERVED 82 GND 84 GND 86 VBAT_RF 88 VBAT_RF 41 RESERVED 39 GND 37 RESERVED 35 GND 33 USB_DM 31 GND 29 USIM_DATA 27 USIM_CLK 23 RESERVED 21 RESERVED 19 RESERVED 17 GND 15 RESERVED 13 GND 11 RESERVED 9 RESERVED 7 RESERVED 40 RESERVED 25 USIM_DET 38 RESERVED 36 USB_ID 3...

Страница 19: ... PI Power supply for the module s baseband part and RF part Vmax 4 3 V Vmin 3 3 V Vnorm 3 8 V It must be provided with a sufficient current of 1 5 A at least VBAT_RF 85 86 87 88 PI Power supply for the module s RF part Vmax 4 3 V Vmin 3 3 V Vnorm 3 8 V It must be provided with a sufficient current of 0 5 A at least 1 VDD_EXT 168 PO Provide 1 8 V for external circuit Vnorm 1 8 V IOmax 50 mA Power s...

Страница 20: ...Indication Interface Pin Name Pin No I O Description DC Characteristics Comment NET_MODE 147 DO Indicate the module s network registration mode VOHmin 1 35 V VOLmax 0 45 V 1 8 V power domain If unused keep it open NET_ STATUS 170 DO Indicate the module s network activity status VOHmin 1 35 V VOLmax 0 45 V 1 8 V power domain If unused keep it open USB Interface Pin Name Pin No I O Description DC Ch...

Страница 21: ...SIM Vmax 3 05 V Vmin 2 75 V IOmax 50 mA Either 1 8 V or 3 0 V is supported by the module automatically USIM_DATA 29 IO U SIM card data For 1 8 V U SIM VILmax 0 36 V VIHmin 1 26 V VOLmax 0 4 V VOHmin 1 45 V For 3 0 V U SIM VILmax 0 57 V VIHmin 2 0 V VOLmax 0 4 V VOHmin 2 3 V USIM_CLK 27 DO U SIM card clock For 1 8 V U SIM VOLmax 0 4 V VOHmin 1 45 V For 3 0 V U SIM VOLmax 0 4 V VOHmin 2 3 V USIM_RST...

Страница 22: ...ILmax 0 6 V VIHmin 1 2 V VIHmax 2 0 V 1 8 V power domain If unused keep it open MAIN_DTR 62 DI Main UART data terminal ready VILmin 0 3 V VILmax 0 6 V VIHmin 1 2 V VIHmax 2 0 V 1 8 V power domain Pull up by default Pulling down to low level will wake up the module If unused keep it open MAIN_TXD 60 DO Main UART transmit VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain If unused keep it open MAIN_RXD...

Страница 23: ...Hmin 1 35 V 1 8 V power domain If unused keep it open PCM_SYNC 65 IO PCM data frame sync VOLmax 0 45 V VOHmin 1 35 V VILmin 0 3 V VILmax 0 6 V VIHmin 1 2 V VIHmax 2 0 V 1 8 V power domain In master mode it is an output signal In slave mode it is an input signal If unused keep it open PCM_CLK 67 IO PCM clock VOLmax 0 45 V VOHmin 1 35 V VILmin 0 3 V VILmax 0 6 V VIHmin 1 2 V VIHmax 2 0 V 1 8 V power...

Страница 24: ...CLK_ P 179 AO PCIe reference clock If unused keep it open PCIE_REFCLK_ M 180 AO PCIe reference clock If unused keep it open PCIE_TX_M 182 AO PCIe transmit If unused keep it open PCIE_TX_P 183 AO PCIe receive If unused keep it open PCIE_RX_M 185 AI PCIe receive If unused keep it open PCIE_RX_P 186 AI PCIe receive If unused keep it open PCIE_CLKREQ _N 188 IO PCIe clock request VOLmax 0 45 V VOHmin 1...

Страница 25: ...gh If unused keep it open COEX_RXD 146 DI LTE WLAN coexistence receive VILmin 0 3 V VILmax 0 6 V VIHmin 1 2 V VIHmax 2 0 V 1 8 V power domain If unused keep it open COEX_TXD 145 DO LTE WLAN coexistence transmit VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain If unused keep it open WLAN_SLP_ CLK 169 DO WLAN sleep clock VOLmax 0 45 V VOHmin 1 35 V If unused keep it open SD Card Interface Pin Name Pin...

Страница 26: ...If unused keep it open RF Interface Pin Name Pin No I O Description DC Characteristics Comment ANT_DRX 127 AI Diversity antenna interface 50 Ω impedance If unused keep it open ANT_MAIN 107 IO Main antenna interface 50 Ω impedance GPIO Interface Pin Name Pin No I O Description DC Characteristics Comment GPIO1 138 IO General purpose input output VOLmax 0 45 V VOHmin 1 35 V VILmin 0 3 V VILmax 0 6 V ...

Страница 27: ... the module into emergency download mode VILmin 0 3 V VILmax 0 6 V VIHmin 1 2 V VIHmax 2 0 V 1 8 V power domain If unused keep it open SLEEP_IND 144 DO Indicate the module s sleep mode VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain If unused keep it open RESERVED Pins Pin Name Pin No I O Description DC Characteristics Comment RESERVED 3 4 6 7 8 9 11 12 14 15 18 23 37 38 40 41 71 74 77 80 91 95 101...

Страница 28: ...erent approaches to setting the module into sleep mode Minimum Functionality Mode Executing AT CFUN 0 command can set the module into minimum functionality mode without removing the power supply In this mode both RF function and U SIM card are invalid Airplane Mode Executing AT CFUN 4 command or driving W_DISABLE pin to low logic level can set the module into airplane mode where the RF function is...

Страница 29: ...t Sleep Mode via UART The module and the host will be waken up in the following conditions Driving the host DTR LOW will wake up the module When the module has a URC to report an RI signal will wake up the host Please refer to Chapter 3 16 for details about RI behavior 3 5 1 2 Set Sleep Mode via USB with Suspend Resume and Remote Wakeup If the host supports USB suspend resume and remote wakeup fun...

Страница 30: ...bus so as to wake up the host 3 5 1 3 Set Sleep Mode via USB with Suspend Resume and RI Function If the host supports USB suspend resume but not remote wake up function the RI signal is needed to wake up the host The following steps are required to set the module into sleep mode Execute AT QSCLK 1 command to enable the sleep mode Ensure the MAIN_DTR is held at high level or keep it open Ensure the...

Страница 31: ...leep mode The following steps are required to this end Execute AT QSCLK 1 command to enable the sleep mode Ensure the MAIN_DTR is held at high level or keep it open Disconnect USB_VBUS The following figure shows the connection between module and host in this case USB_VBUS USB_DP USB_DM VDD USB_DP USB_DM Module Host RI EINT Power Switch GPIO GND GND Figure 7 Sleep Mode without Suspend Function Supp...

Страница 32: ...disabled The W_DISABLE control function is disabled in firmware by default It can be enabled by executing AT QCFG airplanecontrol command which is under development 3 6 Power Supply 3 6 1 Power Supply Pins EG060V EA provides six VBAT pins dedicated to connecting with the external power supply There are two separate voltage domains for these pins Four VBAT_RF pins for module s RF part Two VBAT_BB p...

Страница 33: ...hree ceramic capacitors 100 nF 33 pF 10 pF for composing the MLCC array and place these capacitors close to VBAT pins The main power supply from an external application has to be the single voltage source which supplies power along two sub paths with star structure The width of both VBAT_BB and VBAT_RF traces should be no less than 2 mm In principle the longer the VBAT trace is the wider it should...

Страница 34: ...power supply of EG060V EA should be able to provide a sufficient current of 2 A 1 at least If the voltage drop between the input and output is not too high it is suggested that an LDO should be used while supplying power for the module If there is a big voltage difference between the input source and the desired output VBAT a buck converter is preferred The following figure shows a reference desig...

Страница 35: ... off 3 7 1 Turn on the Module with PWRKEY The following table shows the pin definition of PWRKEY Table 7 Pin Definition of PWRKEY When EG060V EA is in power down mode you can set it into normal mode by driving the PWRKEY pin to a low level for at least 500ms advisably using an open collector driver and release the pin after the STATUS pin outputs high level A reference design is given below Turn o...

Страница 36: ...D protection is indispensable A reference design is given below PWRKEY S1 Close to S1 TVS Figure 12 Turn on the Module with Button The timing of turning on is illustrated in the following figure VIL 1 2 V VIH 2 4 V VBAT PWRKEY 550 ms RESET_N STATUS Inactive Active UART NOTE Inactive Active USB 21 s 26 6 s 14 s Figure 13 Timing of Turning on the Module Please make sure that VBAT is stable for no le...

Страница 37: ...edure OFF Module Status STATUS 30 s Figure 14 Timing of Turning off the Module 3 7 2 2 Turn off the Module with AT Command It is also a safe way to use AT QPOWD command to turn off the module which is similar to turning off the module via the PWRKEY pin Please refer to document 1 for details about the AT QPOWD command 1 In order to avoid damaging internal flash please do not switch off the power s...

Страница 38: ...ended circuit is similar to the PWRKEY control circuit An open collector driver or button can be used to control the RESET_N Reset pulse RESET_N 4 7K 47K 250 600 ms Figure 15 Resetting the Module with Driving Circuit RESET_N S2 Close to S2 TVS Figure 16 Resetting the Module with Button Pin Name Pin No Description DC Characteristics Comment RESET_N 1 Reset the module VIHmax 2 0 V VIHmin 1 3 V VILma...

Страница 39: ...command or the PWRKEY pin 2 Ensure that there is no large capacitance on PWRKEY and RESET_N pins 3 9 U SIM Interface The U SIM interface circuitry meets ETSI and IMT 2000 requirements Either 1 8 V or 3 0 V U SIM cards is supported Table 9 Pin Definition of U SIM Interface Pin Name Pin No I O Description Comment USIM_VDD 26 PO U SIM card power supply Either 1 8 V or 3 0 V is supported by the module...

Страница 40: ...ATA USIM_DET 22R 22R 22R VDD_EXT 51K 100 nF U SIM Card Connector GND GND VCC RST CLK IO VPP GND USIM_VDD 15K NM NM NM Figure 18 Reference Design of U SIM Interface with 8 Pin U SIM Card Connector If U SIM card detection function is not needed please keep USIM_DET disconnected A reference design for U SIM interface with a 6 pin U SIM card connector is shown below Module USIM_VDD USIM_GND USIM_RST U...

Страница 41: ...n module and U SIM card Additionally keep the U SIM peripheral circuit close to the U SIM card connector The pull up resistor on USIM_DATA line can improve anti jamming capability in sensitive occasions or when long traces are applied and should be placed close to the U SIM card connector 3 10 USB Interface EG060V EA provides one integrated Universal Serial Bus USB interface which complies with th...

Страница 42: ...extra stubs of trace must be as short as possible To meet USB 2 0 specifications the following principles should be complied with while designing the USB interface It is important to route the USB signal traces as a differential pair with total grounding Keep the impedance of the pair at 90 Ω Do not route signal traces under crystals oscillators magnetic devices PCIe and RF signal traces Route the...

Страница 43: ...aud rate It is used for Linux console and log output The following tables show the pin definition Table 11 Pin Definition of the Main UART Interface Table 12 Pin Definition of the Debug UART Interface Pin Name Pin No I O Description Comment MAIN_RI 61 DO Main UART ring indication 1 8 V power domain MAIN_DCD 59 DO Main UART data carrier detect 1 8 V power domain MAIN_CTS 56 DO Main UART clear to se...

Страница 44: ...MAIN_RXD MAIN_DTR MAIN_CTS MAIN_TXD 51K 51K 0 1 μF 0 1 μF RI_MCU DCD_MCU RTS_MCU TXD_MCU DTR_MCU CTS_MCU RXD_MCU VDD_MCU Translator VDD_EXT 10K 120K Figure 21 Reference Design of Translator Chip Please visit http www ti com for more information on the recommended translator Another approach to level translation is with a transistor translation circuit A reference design in this regard is shown bel...

Страница 45: ...CTS and MAIN_RTS are connected respectively to the host CTS and RTS 3 12 PCM and I2C Interfaces EG060V EA supports audio communication via Pulse Code Modulation PCM digital interface and I2C interface The PCM interface supports the following mode Primary mode short frame synchronization the module works as both master and slave In the primary mode the data is sampled on the falling edge of the PCM...

Страница 46: ...s Clock and mode can be configured by AT command and the default configuration is master mode using Pin Name Pin No I O Description Comment PCM_DIN 66 DI PCM data input 1 8 V power domain If unused keep it open PCM_DOUT 68 DO PCM data output 1 8 V power domain If unused keep it open PCM_SYNC 65 IO PCM data frame sync 1 8 V power domain In master mode it is an output signal In slave mode it is an i...

Страница 47: ...N LOUTP LOUTN Codec Figure 24 Reference Design of PCM Interface with Audio Codec 1 It is recommended to reserve an RC R 22 Ω C 22 pF circuit on the PCM lines especially for PCM_CLK 2 EG060V EA works as a master device pertaining to I2C interface 3 13 ADC Interfaces The module provides two Analog to Digital Converters ADC interfaces AT QADC 0 command and AT QADC 1 command can be used respectively t...

Страница 48: ...DE and NET_STATUS can be used to drive network status indication LEDs Their definitions and logic level changes upon the switch of network mode status are described in the following tables Table 17 Pin Definition of Network Mode Status Indication Pins Pin Name Pin No Description DC Characteristics ADC0 173 General purpose ADC interface Voltage range 0 to 1 4 V ADC1 175 General purpose ADC interfac...

Страница 49: ...tor 3 15 Module Status Indication Interface The STATUS pin is used to indicate the module s on or off status It outputs high level when the module is turned on Pin Name Status Description NET_MODE Always High Registered on LTE network Always Low Other circumstances NET_STATUS LEDs flicker slowly 200 ms High 1800 ms Low Network searching LEDs flicker slowly 1800 ms High 200 ms Low Idle LEDs flicker...

Страница 50: ...Design of STATUS 3 16 RI Behaviors The AT QCFG risignaltype physical command can be used to configure RI behavior Regardless of from which port a URC is output it triggers the behavior of the RI pin The URC can be output from UART port USB AT port or USB modem port depending on the parameters of AT QURCCFG command The default port is USB AT port Pin Name Pin No I O Description Comment STATUS 171 D...

Страница 51: ...tion to an external Ethernet IC MAC and PHY or WLAN IC The following table shows the pin definition of PCIe interface Table 21 Pin Definition of PCIe Interface State Response Idle RI stays at high level URC RI outputs 120 ms low pulse when a new URC returns Pin Name Pin No I O Description Comment PCIE_REFCLK_P 179 AO Output PCIe reference clock If unused keep it open PCIE_REFCLK_M 180 AO Output PC...

Страница 52: ...or crossing other traces means under development 3 18 WLAN Control Interface EG060V EA provides a low power PCIe interface and a control interface for WLAN design The following table shows the pin definition of WLAN control interface Table 22 Pin Definition of WLAN Control Interface If unused keep it open PCIE_RST_N 189 IO PCIe reset In master mode it is an output signal In slave mode it is an inp...

Страница 53: ...TXD 145 DO LTE WLAN coexistence transmit 1 8 V power domain WLAN_SLP_CLK 169 DO WLAN sleep clock 1 8 V power domain Pin Name Pin No I O Description Comment SDIO_DATA3 48 IO SDIO data bit 3 SDIO_DATA2 47 IO SDIO data bit 2 SDIO_DATA1 50 IO SDIO data bit 1 SDIO_DATA0 49 IO SDIO data bit 0 SDIO_CLK 53 DO SD card clock SDIO_CMD 51 IO SD card command SDIO_VDD 46 PO SDIO power supply 1 8 2 85 V configur...

Страница 54: ...tors is among 10 100 kΩ and the recommended value is 100 kΩ In order to improve signal quality it is recommended to add 0 ohm resistors R1 R6 in series between the module and the SD card The bypass capacitors C1 C6 are reserved and not mounted by default All resistors and bypass capacitors should be placed close to the module In order to offer good ESD protection it is recommended to add a TVS dio...

Страница 55: ...iming of SPI interface The related parameters of SPI timing are shown in the following table SPI_CS_N SPI_CLK SPI_MOSI MSB 1 2 SPI_MISO 3 T t mov 4 t mis t mih t ch t cl Figure 28 SPI Interface Timing Table 25 Parameters of SPI Interface Timing Pin Name Pin No I O Description Comment SPI_CS 166 DO SPI chip select 1 8 V power domain If unused keep them open SPI_MOSI 163 DO SPI master out SPI_MISO 1...

Страница 56: ...29 Reference Design of SPI Interface with Level Translator 3 21 USB_BOOT Interface EG060V EA provides a USB_BOOT interface Developers can pull up USB_BOOT to VDD_EXT before powering on the module thus the module will enter into emergency download mode when powered on In this mode the module supports firmware upgrade over USB interface Table 26 Pin Definition of USB_BOOT Interface t cl SPI clock lo...

Страница 57: ...s EG060V EA Hardware Design EG060V EA_Hardware_Design 56 82 Below is a reference design of USB_BOOT interface Module USB_BOOT VDD_EXT 4 7 k Test point TVS Close to module Figure 30 Reference Design of USB_BOOT Interface ...

Страница 58: ...efinition The pin definition of main antenna and Rx diversity antenna interfaces are shown as below Table 27 Pin Definition of RF Antenna 4 1 2 Operating Frequency Table 28 EG060V EA Operating Frequencies Pin Name Pin No I O Description Comment ANT_MAIN 107 IO Main antenna interface 50 Ω impedance ANT_DRX 127 AI Diversity antenna interface 50 Ω impedance 3GPP Band Transmit Receive Unit WCDMA B1 19...

Страница 59: ... Main Antenna NM C2 NM R2 0R C3 Diversity Antenna NM C4 NM ANT_DRX Figure 31 Reference Design of RF Antenna Interface 1 Keep a proper distance between the main and the Rx diversity antenna to improve the receiving sensitivity 2 Place the π type matching components R1 C1 C2 and R2 C3 C4 as close to the antenna as possible LTE B7 2500 2570 2620 2690 MHz LTE B8 880 915 925 960 MHz LTE B20 832 862 791...

Страница 60: ...c constant the height from the reference ground to the signal layer H and the spacing between RF traces and grounds S Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance The following are reference designs of microstrip or coplanar waveguide with different PCB structures Figure 32 Reference Design of Microstrip on 2 layer PCB Figure 33 Reference Desi...

Страница 61: ... ground The distance between the RF pins and the RF connector should be as short as possible and all the right angle traces should be changed to curved ones There should be clearance area under the signal pin of the antenna connector or solder joint The reference ground of RF traces should be complete Meanwhile adding some ground vias around RF traces and the reference ground can help improve RF p...

Страница 62: ...Installation If an RF connector is needed for antenna connection the U FL R SMT connector provided by Hirose is recommended Figure 36 Dimensions of U FL R SMT Connector Unit mm Type Requirements WCDMA LTE VSWR 2 Efficiency 30 Max Input Power 50 W Input Impedance 50 Ω Cable Insertion Loss 1 dB WCDMA B5 B6 B8 B19 LTE B5 B8 B12 B13 B18 B19 B20 B26 B28 B29 Cable Insertion Loss 1 5 dB WCDMA B1 B2 B3 B4...

Страница 63: ...ies listed in the following figure can be used to match the U FL R SMT Figure 37 Mechanical Features of U FL LP Connectors The following figure illustrates the space factor of mated connectors Figure 38 Form Factor of Mated Connectors Unit mm For more details please visit https www hirose com lang en ...

Страница 64: ... voltage on digital and analog pins of the module are listed in the following table Table 30 Absolute Maximum Ratings 1 The current consumption is tested in 3G 4G instead of 2G environment Item Min Max Unit VBAT_RF VBAT_BB 0 3 4 7 V USB_VBUS 0 3 5 5 V Peak Current of VBAT_BB 0 1 5 A Peak Current of VBAT_RF 0 0 3 1 A Voltage at Digital Pins 0 3 2 3 V Voltage at ADC0 0 1 4 V Voltage at ADC1 0 1 4 V ...

Страница 65: ...e radio spectrum or harm to radio networks Only one or more parameters like Pout might reduce in the value and exceed the specified tolerances When the temperature returns to normal operating temperature levels the module will meet 3GPP specifications again 3 It is not recommended to use the module without adopting a heat dissipation component Tests are conducted at all temperature levels with hea...

Страница 66: ...ted 4 854 mA LTE FDD PF 128 USB disconnected 3 643 mA LTE TDD PF 32 USB disconnected 7 781 mA LTE TDD PF 64 USB disconnected 4 984 mA LTE TDD PF 128 USB disconnected 3 539 mA Idle state WCDMA PF 64 USB disconnected 29 29 mA WCDMA PF 64 USB connected 42 99 mA LTE FDD PF 64 USB disconnected 29 87 mA LTE FDD PF 64 USB connected 43 61 mA LTE TDD PF 64 USB disconnected 29 89 mA LTE TDD PF 64 USB connec...

Страница 67: ...78 dBm 451 mA LTE TDD B40 CH39150 23 00 dBm 444 mA LTE TDD B41 CH40740 22 91 dBm 413 mA 2 CA data transfer LTE FDD B1 B1 23 02 dBm 840 mA LTE FDD B1 B3 22 75 dBm 868 mA LTE FDD B1 B5 22 75 dBm 806 mA LTE FDD B1 B8 22 74 dBm 819 mA LTE FDD B1 B20 22 75 dBm 849 mA LTE FDD B1 B28 22 73 dBm 851 mA LTE FDD B3 B3 21 73 dBm 786 mA LTE FDD B3 B5 22 71 dBm 810 mA LTE FDD B3 B7 22 71 dBm 842 mA LTE FDD B3 B...

Страница 68: ... transmitting power is 21 5 dBm 1 dB LTE FDD B7 B28 22 03 dBm 855 mA LTE TDD B38 B38 21 75 dBm 490 mA LTE TDD B40 B40 21 86 dBm 467 mA LTE TDD B41 B41 21 79 dBm 484 mA WCDMA voice call WCDMA B1 CH10700 22 53 dBm 545 mA WCDMA B5 CH4407 22 66 dBm 485 mA WCDMA B8 CH3012 22 83 dBm 532 mA Frequency Max Min WCDMA bands 24 dBm 1 3 dB 50 dBm LTE FDD bands 23 dBm 2 Db 1 40 dBm LTE TDD bands 23 dBm 2 dB 40 ...

Страница 69: ...equently it is subject to ESD handling precautions that typically apply to ESD sensitive components Proper ESD handling and packaging procedures must be applied throughout the processing handling and operation of any Frequency Primary Diversity SIMO 1 3GPP SIMO WCDMA B1 109 5 106 7 WCDMA B5 109 5 104 7 WCDMA B8 109 5 103 7 LTE FDD B1 10 MHz 97 97 100 5 96 3 LTE FDD B3 10 MHz 97 96 5 100 5 93 3 LTE...

Страница 70: ...rea where the module is mounted and do not cover that area with copper allowing for the adding of heatsink when necessary Ensure the reference ground of the area where the module is mounted is complete and add as many ground vias as possible for better heat dissipation Make sure the ground pads of the module and PCB are fully connected According to particular application demands mount the heatsink...

Страница 71: ...Design of Heatsink Heatsink at the Top of the Module Thermal Pad Heatsink Application Board Application Board Heatsink Thermal Pad Module Shielding Cover Figure 40 Reference Design of Heatsink Heatsink at the Backside of PCB 1 Make sure that your PCB design provides sufficient cooling for the module proper mounting heatsinks and active cooling may be required depending on the integrated applicatio...

Страница 72: ...0V EA_Hardware_Design 71 82 possible extent to maintain the module s internal temperature below 105 C You can execute the AT QTEMP command to get the module s internal temperature 3 For more detailed guides on thermal design please refer to document 5 ...

Страница 73: ...hanical Dimensions This chapter describes the mechanical dimensions of the module All dimensions are measured in millimeter mm and the dimensional tolerances are 0 05 mm unless otherwise specified 6 1 Mechanical Dimensions of the Module Figure 41 Top and Side Dimensions of the Module ...

Страница 74: ... Module Series EG060V EA Hardware Design EG060V EA_Hardware_Design 73 82 Figure 42 Bottom Dimensions Bottom View of the Module The package warpage level of the module conforms to JEITA ED 7306 standard NOTE ...

Страница 75: ... Hardware Design EG060V EA_Hardware_Design 74 82 6 2 Recommended Footprint Figure 43 Recommended Footprint Top View For easy maintenance of the module keep about 3 mm between the module and other components on the motherboard NOTE ...

Страница 76: ...G060V EA_Hardware_Design 75 82 6 3 Renderings of the Module Figure 44 Top View of the Module Figure 45 Bottom View of the Module These are renderings of EG060V EA module For authentic appearance please refer to the module received from Quectel NOTE ...

Страница 77: ...e module must be processed in reflow soldering or other high temperature operations within 168 hours Otherwise the module should be stored in an environment where the relative humidity is less than 10 e g a drying cabinet 4 The module should be pre baked to avoid blistering cracks and inner layer separation in PCB under the following circumstances The module is not stored in Recommended Storage Co...

Страница 78: ...sired please refer to IPC JEDEC J STD 033 for baking procedure 7 2 Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil thus making the paste fill the stencil openings and then penetrate to the PCB The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass To ensure the module soldering quality the th...

Страница 79: ...C s Max slope 2 3 C s Figure 46 Recommended Reflow Soldering Thermal Profile Table 37 Recommended Thermal Profile Parameters Factor Recommendation Soak Zone Max slope 1 3 C s Soak time between A and B 150 C and 200 C 70 120 s Reflow Zone Max slope 2 3 C s Reflow time D over 220 C 45 70 s Max temperature 238 C to 246 C Cooling down slope 1 5 to 3 C s Reflow Cycle Max reflow cycle 1 ...

Страница 80: ...Hardware_Design 79 82 7 3 Packaging EG060V EA is packaged in tape and reel carriers One reel is 10 56 meters long and contains 200 modules The figures below show the packaging details measured in mm Figure 47 Tape Specifications Figure 48 Reel Specifications ...

Страница 81: ...60V EA_Reference_Design EG060V EA Reference Design 4 Quectel_RF_Layout_Application_Note RF Layout Application Note 5 Quectel_Module_Thermal_Design_Guide Thermal Design Guide for Quectel modules Abbreviation Description AMR Adaptive Multi rate bps Bits per Second CHAP Challenge Handshake Authentication Protocol CS Coding Scheme CTS Clear to Send DL Downlink DTR Data Terminal Ready ESD Electrostatic...

Страница 82: ...ultiple Input Multiple Output MO Mobile Originated MS Mobile Station MT Mobile Terminated PAP Password Authentication Protocol PCB Printed Circuit Board PCC Primary Carrier Component PDU Protocol Data Unit PPP Point to Point Protocol QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency Rx Receive SCC Secondary Carrier Component SIMO Single Input Multiple Output...

Страница 83: ...Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VImax Absolute Maximum Input Voltage Value VImin Absolute Minimum Input Voltage Value VOHmax Maximum Output High Level Voltage Value VOHmin Minimum Output High Level Voltage Value VOLmax Maximum Output Low Level Voltage Value VOLmin Minimum Output Low Level Voltage Value VSWR Vo...

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