LTE Standard Module Series
EC25 Mini PCIe Hardware Design
EC25_Mini_PCIe_Hardware_Design 27 / 79
USB_DP
USB_DM
GND
USB_DP
USB_DM
GND
L1
Close to Module
R3
R4
Test Points
NM_0R
NM_0R
Minimize these stubs
Module
MCU
ESD Array
Figure 6: Reference Circuit of USB Interface
A common mode choke L1 is recommended to be added in series between the module and customer’s
MCU in order to suppress EMI spurious transmission. Meanwhile, the 0Ω resistors (R3 and R4) should be
added in series between the module and the test points so as to facilitate debugging, and the resistors are
not mounted by default. In order to ensure the integrity of USB data line signal, L1/R3/R4 components
must be placed close to the module, and also these resistors should be placed close to each other. The
extra stubs of trace must be as short as possible.
The following principles should be complied with when design the USB interface, so as to meet USB 2.0
specification.
It is important to route the USB signal traces as differential pairs with total grounding. The impedance
of USB differential trace is 90
Ω.
Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is
important to route the USB differential traces in inner layer with ground shielding on not only upper
and lower layers but also right and left sides.
Keep the ESD protection components to the USB connector as close as possible.
3.8. UART Interfaces
The following table shows the pin definition of the main UART and COEX UART* interfaces.
3.8.1. Main UART Interface
The main UART interface supports 9600bps, 19200bps, 38400bps, 57600bps, 115200bps and
230400bps baud rates, and the default is 115200bps. This interface supports RTS and CTS hardware
flow control, and be used for AT command communication and data transmission.