Transistor c
3.12. PC
EC25 provid
following mo
Primary
Auxiliar
In primary m
edge; the P
1024 and20
In auxiliary
edge; while
128kHz PC
EC25 supp
theprimary
auxiliary mo
NOTE
E
MCU/A
circuit solutio
CM and I2
des one Pu
odes:
y mode (sho
ry mode (lon
mode, the d
CM_SYNC
048kHz for d
mode, the d
the PCM_S
M_CLK and
orts 8-bit A
mode’s tim
ode’s timing
EC25-A_Us
ARM
/TXD
/RXD
/RTS
/CTS
GPIO
GPIO
EINT
GND
Figure 21
on is not suit
2C Interfa
lse Code M
ort sync, wor
ng sync, wor
ata is samp
falling edge
different spe
data is samp
SYNC rising
d an 8kHz, 5
A-law and
μ
-l
ming relation
relationship
ser_ManualC
10K
VCC_MCU
VDD_EXT
1: Referenc
table for hig
ace
odulation (P
rks as both
rks as maste
pled on the f
represents
ech codecs
pled on the f
edge repres
50% duty cyc
aw, and als
nship with 8
p with 8kHz
Confidentia
V
4.7K
4.7K
1nF
1nF
e Circuit wi
h baud rate
PCM) digital
master and
er only)
falling edge
the MSB. In
.
falling edge
sents the MS
cle PCM_SY
so 16-bit lin
8kHz PCM_
PCM_SYNC
al / Release
VDD_EXT
10K
VDD_EXT
ith Transist
s exceeding
interface fo
slave)
of the PCM
n this mode,
of the PCM
SB. In this m
YNC only.
near data fo
_SYNC and
C and 128kH
d 38 / 6
TXD
RXD
RTS
CTS
DTR
RI
GND
DCD
Mo
tor Circuit
g 460Kbps.
or audio des
M_CLK and t
PCM_CLK
M_CLK and t
mode, PCM i
ormats. The
d 2048kHz
Hz PCM_CL
L
EC25-AU
69
odule
sign, which s
transmitted o
supports 12
transmitted
nterface ope
following f
PCM_CLK,
LK.
LTE Module
ser Manua
supports the
on the rising
28, 256, 512
on the rising
erates with a
igures show
as well as
e
al
e
g
2,
g
a
w
s
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