Quatech DS-1000, Руководство пользователя

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I I I . 1 6 5 5 0 F U N C T I O N A L D E S C R I P T I O N
T h e 1 6 5 5 0 i s a n u p g r a d e o f t h e s t a n d a r d 1 6 4 5 0
A s y n c h r o n o u s C o m m u n i c a t i o n s E l e m e n t ( A C E ) . D e s i g n e d t o b e
compatible with the 16450, the 16550 enters the character mode
o n r e s e t a n d i n t h i s m o d e w i l l a p p e a r a s a 1 6 4 5 0 t o u s e r
s o f t w a r e . A n a d d i t i o n a l m o d e , F I F O m o d e , c a n b e s e l e c t e d t o
r e d u c e C P U o v e r h e a d a t h i g h d a t a r a t e s . T h e F I F O m o d e
i n c r e a s e s p e r f o r m a n c e b y p r o v i d i n g t w o i n t e r n a l 1 6 - b y t e F I F O s
( o n e t r a n s m i t a n d o n e r e c e i v e ) t o b u f f e r d a t a a n d r e d u c e t h e
number of interrupts issued to the CPU.
Other features include:
P r o g r a m m a b l e b a u d r a t e , c h a r a c t e r l e n g t h , p a r i t y ,
and number of stop bits
A u t o m a t i c a d d i t i o n a n d r e m o v a l o f s t a r t , s t o p , a n d
parity bits
I n d e p e n d e n t a n d p r i o r i t i z e d t r a n s m i t , r e c e i v e a n d
status interrupts
Transmitter clock output to drive receiver logic
T h e f o l l o w i n g p a g e s p r o v i d e a b r i e f s u m m a r y o f t h e
i n t e r n a l r e g i s t e r s a v a i l a b l e w i t h i n t h e 1 6 5 5 0 A C E . T h e
registers are addressed as shown in Figure 2 below.
+---------------+----------------------------------------+
| DLAB A2 A1 A0 | REGISTER DESCRIPTION |
+---------------+----------------------------------------+
| 0 0 0 0 | Receive buffer (read only) |
| | Transmit holding register (write only) |
| 0 0 0 1 | Interrupt enable |
| x 0 1 0 | Interrupt identification (read only) |
| | FIFO control (write only) |
| x 0 1 1 | Line control |
| x 1 0 0 | MODEM control |
| x 1 0 1 | Line status |
| x 1 1 0 | MODEM status |
| x 1 1 1 | Scratch |
| 1 0 0 0 | Divisor latch (least significant byte) |
| 1 0 0 1 | Divisor latch (most significant byte) |
+---------------+----------------------------------------+
F i g u r e 2 . I n t e r n a l r e g i s t e r m a p f o r 1 6 5 5 0 A C E . D L A B i s
accessed through the Line Control Register.
iv