Quatech DS-1000, Руководство пользователя

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I I I C . F I F O C O N T R O L R E G I S T E R
+------+
D7 | RXT1 |--+
+------+ +-- Receiver trigger
D6 | RXT0 |--+
+------+
D5 | x |--+
+------+ +-- Reserved
D4 | x |--+
+------+
D3 | DMAM |----- DMA mode select
+------+
D2 | XRST |----- Transmit FIFO reset
+------+
D1 | RRST |----- Receive FIFO reset
+------+
D0 | FE |----- FIFO enable
+------+
Figure 6. FIFO control register bit definitions.
RXTx - Receiver FIFO Trigger Level:
D e t e r m i n e s t h e t r i g g e r l e v e l f o r t h e F I F O i n t e r r u p t a s
given in Figure 7 below.
+-----------+-----------------------+
| | RCVR FIFO |
| RXT1 RXT0 | Trigger level (bytes) |
+-----------+-----------------------+
| 0 0 | 1 |
| 0 1 | 4 |
| 1 0 | 8 |
| 1 1 | 14 |
+-----------+-----------------------+
Figure 7. FIFO trigger levels.
DMAM - DMA Mode Select:
When set (logic 1), RxRDY and TxRDY change from mode 0
to mode 1. (DMA mode not supported on DS-1000)
XRST - Transmit FIFO Reset:
W h e n s e t ( l o g i c 1 ) , a l l b y t e s i n t h e t r a n s m i t t e r F I F O
a r e c l e a r e d a n d t h e c o u n t e r i s r e s e t . T h e s h i f t
register is not cleared. XRST is self-clearing.
RRST - Receive FIFO Reset:
When set (logic 1), all bytes in the receiver FIFO are
c l e a r e d a n d t h e c o u n t e r i s r e s e t . T h e s h i f t r e g i s t e r
is not cleared. RRST is self-clearing.
FE - FIFO Enable:
W h e n s e t ( l o g i c 1 ) , e n a b l e s t r a n s m i t t e r a n d r e c e i v e r
F I F O s . W h e n c l e a r e d ( l o g i c 0 ) , a l l b y t e s i n b o t h
F I F O s a r e c l e a r e d . T h i s b i t m u s t b e s e t w h e n o t h e r
b i t s i n t h e F I F O c o n t r o l r e g i s t e r a r e w r i t t e n t o o r
the bits will be ignored.
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