I I I H . S C R A T C H P A D R E G I S T E R
This register is not used by the 16550. It may be used
by the programmer for data storage.
I V . F I F O I N T E R R U P T M O D E O P E R A T I O N
1. The receive data interrupt is issued when
the FIFO reaches the trigger level. The
interrupt is cleared as soon as the FIFO
falls below the trigger level.
2 . T h e i n t e r r u p t i d e n t i f i c a t i o n r e g i s t e r ' s
r e c e i v e d a t a a v a i l a b l e i n d i c a t o r i s s e t
a n d c l e a r e d a l o n g w i t h t h e r e c e i v e d a t a
interrupt above.
3 . T h e d a t a r e a d y i n d i c a t o r i s s e t a s s o o n
a s a c h a r a c t e r i s t r a n s f e r r e d i n t o t h e
r e c e i v e r F I F O a n d i s c l e a r e d w h e n t h e
FIFO is empty.
V . D I V I S O R L A T C H V A L U E S
+-----------+-------------+-----------------------+
| Desired | Divisor | Error Between Desired |
| Baud Rate | Latch Value | and Actual Value (%) |
+-----------+-------------+-----------------------+
| 50 | 2304 | - |
| 75 | 1536 | - |
| 110 | 1047 | 0.026 |
| 150 | 768 | - |
| 300 | 384 | - |
| 600 | 192 | - |
| 1200 | 96 | - |
| 1800 | 64 | - |
| 2000 | 58 | 0.69 |
| 2400 | 48 | - |
| 3600 | 32 | - |
| 4800 | 24 | - |
| 7200 | 16 | - |
| 9600 | 12 | - |
| 19200 | 6 | - |
| 38400 | 3 | - |
| 56000 | 2 | 2.86 |
+-----------+-------------+-----------------------+
F i g u r e 1 4 . D i v i s o r l a t c h s e t t i n g s f o r c o m m o n b a u d r a t e s
using a 1.8432 Mhz crystal.
iv
Содержание DS-1000
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