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QM_Spartan-7 Development Board

User Manual V01

3.

Reference

[1]  ug470_7Series_Config.pdf
[2]  ds181_Artix_7_Data_Sheet.pdf
[3]  ug475_7Series_Pkg_Pinout.pdf
[4]  n25q_64a_3v_65nm.pdf
[5]  MP2359.pdf
[6]  NCP1529-D.PDF

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Содержание XILINX SPARTAN-7

Страница 1: ...mall form factor packaging to meet the most stringent requirements These devices feature a MicroBlaze soft processor running over 200 DMIPs with 800Mb s DDR3 support built on 28nm technology Additiona...

Страница 2: ...OLS 4 2 2 QM_SPARTAN 7 HARDWARE DESIGN 7 2 2 1 QM_Spartan 7 Power Supply 7 2 2 1 QM_Spartan 7 3 3V Power Supply 8 2 2 2 QM_Spartan 7 SPI Boot 9 2 2 3 QM_Spartan 7 System Clock 10 2 2 4 QM_Spartan 7 JT...

Страница 3: ...PGA external crystal frequency 50MHz XC7S15 1FTGB196C has rich block RAM resource up to 360Kb XC7S15 1FTGB196C has 12 800 logic cells On Board N25Q064 SPI Flash 8M bytes for user configuration code On...

Страница 4: ...illimeter mm Figure 2 1 QM_Spartan 7 Development Board Dimension 2 1 Install Development Tools The QM_Spartan 7 development board tool chain consists of Xilinx Vivado 2018 2 Xilinx USB platform cable...

Страница 5: ...opment board Figure 2 3 JTAG Connection and Power Supply Once the FPGA test program is correctly Synthesized Implemented and Generated with Bitstream users may click the Open Target option to connect...

Страница 6: ...the Bitstream bit into FPGA or to choose Add Configuration Memory Device to program the mcs file into on board SPI flash Figure 2 5 Program FPGA Users could convert the bit file into the mcs file by...

Страница 7: ...r the FPGA 3V3 1V0 1V0 1V8 XC7S15 1FTGB196 U1D VCCAUX_1 F10 VCCAUX_2 H10 VCCAUX_3 K10 VCCAUX_4 L9 VCCINT_1 D6 VCCINT_2 D8 VCCINT_3 E7 VCCINT_4 E9 VCCINT_5 F6 VCCINT_6 G9 VCCINT_7 H6 VCCINT_8 J9 VCCINT...

Страница 8: ...applied on the board Below image shows the MP2359 hardware design Figure 2 8 MP2359 Hardware Design Figure 2 9 1 0V Core Voltage DC DC R1 100K R3 33K C5 100nF U2 MP2359 BST 1 GND 2 FB 3 EN 4 VIN 5 SW...

Страница 9: ...tings The LED D2 will be turned on after the FPGA successfully loading configuration file from SPI Flash during power on stage In this case LED D2 could be used as FPGA loading status indicator FPGA_D...

Страница 10: ...image shows the detailed hardware design Figure 2 14 50MHz System Clock 2 2 4 QM_Spartan 7 JTAG Port The on board JTAG port uses 6P 2 54mm pitch header which could be easily connected to Xilinx USB p...

Страница 11: ...Ds 2 2 6 QM_Spartan 7 Extension IO The development board has two 50P 2 54mm pitch headers which are used for extending user modules such as ADC DAC module audio video module ethernet module etc 3V3 R1...

Страница 12: ...2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 IO_B13 IO_B14 IO_D12 IO_D13 IO_C14 IO_A12 IO_A13 JP2 HDR_25X2...

Страница 13: ...are required for development Below figure shows the hardware design of CP2102 GMR on the QM_Spartan 7 Figure 2 19 UART Port KEY0 SW2 1 2 nRESET 3V3 R16 4 7k SW1 1 2 SW3 1 2 PROG_B R17 4 7K 3V3 3V3 R15...

Страница 14: ...QM_Spartan 7 Development Board User Manual V01 3 Reference 1 ug470_7Series_Config pdf 2 ds181_Artix_7_Data_Sheet pdf 3 ug475_7Series_Pkg_Pinout pdf 4 n25q_64a_3v_65nm pdf 5 MP2359 pdf 6 NCP1529 D PDF...

Страница 15: ...QM_Spartan 7 Development Board User Manual V01 4 Revision Doc Rev Date Comments 0 1 05 12 2018 Initial Version 1 0 05 12 2018 V1 0 Formal Release...

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