QM_Spartan-7 Development Board
User Manual V01
2.2
QM_Spartan-7 Hardware Design
2.2.1
QM_Spartan-7 Power Supply
The
development
board needs 5V DC input as power supply which could be directly injected from JP1/JP2
header or the Mini USB connector. Users may refer to the hardware schematic for the detailed design. The on
board LED D5 indicates the 3.3V supply, it will be turned on when the 5V power supply is active. In default
status, all the FPGA banks IO power level is 3.3V because bank power supply is 3.3V. Detailed design refer to
hardware schematic.
Note: FPGA core supply 1.0V is regulated by On-Semi DC/DC chip NCP1529 which could output maximum 1A
current.
Figure 2-7. Power Supply for the FPGA
3V3
1V0
1V0
1V8
XC7S15-1FTGB196
U1D
VCCAUX_1
F10
VCCAUX_2
H10
VCCAUX_3
K10
VCCAUX_4
L9
VCCINT_1
D6
VCCINT_2
D8
VCCINT_3
E7
VCCINT_4
E9
VCCINT_5
F6
VCCINT_6
G9
VCCINT_7
H6
VCCINT_8
J9
VCCINT_9
K6
VCCINT_10
K8
VCCO_0_1
N6
VCCO_0_2
N8
VCCO_14_1
G13
VCCO_14_2
K13
VCCO_14_3
N13
VCCO_14_4
G2
VCCO_14_5
K2
VCCO_14_6
N2
VCCBRAM_1
E5
VCCBRAM_2
G5
VCCBRAM_3
J5
XC7S15-1FTGB196
U1E
GND_1
A1
GND_2
A6
GND_3
A9
GND_4
A11
GND_5
A14
GND_6
B4
GND_7
B7
GND_8
B9
GND_9
C2
GND_10
C6
GND_11
C7
GND_12
C8
GND_13
C9
GND_14
C13
GND_15
D5
GND_16
D7
GND_17
D9
GND_18
D11
GND_19
E1
GND_20
E3
GND_21
E6
GND_22
E8
GND_23
E10
GND_24
E14
GND_25
F5
GND_26
F9
GND_27
G3
GND_28
G6
GND_29
G10
GND_30
G12
GND_31
H5
GND_32
H9
GND_33
J6
GND_34
J10
GND_35
K1
GND_36
K5
GND_37
K7
GND_38
K9
GND_39
K14
GND_40
L4
GND_41
L6
GND_42
L8
GND_43
L10
GND_44
L11
GND_45
N3
GND_46
N5
GND_47
N9
GND_48
N12
GND_49
P1
GND_50
P14
