Owner’s Reference
DirectStream DAC
©2014 PS Audio Inc. All rights reserved.
Introduction
15-061-01-1
4826 Sterling Drive, Boulder, CO 80301
Rev A
PH: 720.406.8946 [email protected] www.psaudio.com
Introduction
they can possibly go without causing problems; we also
control their transition times, thus limiting the amount of
induced noise and jitter into the main digital processing
area.
6. Outputs of the FPGA use the slowest, lowest drive
compatible with their function keeping noise as low as
possible.
7. We use slower, older technology CMOS when we need
CMOS. This choice lowers both noise and jitter potential.
8. We use balanced signals when practical, they not only
lessen radiation and are less sensitive to radiation, but they
lessen noise in the ground and power rails.
9. We use non-saturation logic so the exact transitions are
more predictable. Coming out of saturation is a statistical
process.
10. High rate signals (or signals with fast edges) are isolated
from control signals and especially each other. If they have
to be fast they are terminated appropriately to help address
jitter.
11. Jitter is addressed everywhere in the design. Every
component choice, every signal connection, every wire
routed on the boards are all hand done to lower noise and
pay attention to jitter.
12. 0.1% precision thin fi lm low temperature coeffi cient
resistors are incorporated everywhere in the audio path.
2% fi lm caps in critical places and 5% fi lm caps elsewhere
in the audio path. By using 1/8W resistors or 1/4W
resistors where others might use a 1/10W resistor the
temperature coeffi cient of the resistors are lowered. For
digital bypassing NP0/C0G or at worst X7R MLCCs are
used.
13. Low noise techniques are employed such as liberal use of
low inductance capacitor bypassing with a self resonance
frequency at the main clock rate to keep noise from ever
getting into the voltage rails in the fi rst place.
14. Digital fi ltering in general, and the upsampling and noise
Balanced
design
Jitter is
reduced
thoughout the
design
vi
