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16
3
11
In this mode the external RAM memory and the Ethernet controller are not
accessible. SEL outputs operate normally.
Memory maps for modes 1..3 are shown in the picture below:
Mode 0
FFFF
FF00
MMnet102
FEFF
9000
Not used
8FFF
8000
LAN91C111
7FFF
0000
Non banked
RAM and int.
RAM of the uC
32kB
Mode 1
FFFF
FF00
MMnet102
FEFF
C01F
Not used
C01E
C000
LAN91C111
BFFF
8000
Banked
RAM
16kB
7FFF
0000
Non banked
RAM and int.
RAM of the uC
32kB
Mode 2
FFFF
FF00
MMnet102
FEFF
0000
Non banked
RAM and int.
RAM of the uC
65280B
The remaining bits of the configuration register serve to set the operating mode of the SEL outputs and their
polarization.
Mode SEL1CFG1..0
Description
0
00
Write strobe.
A pulse is generated at the moment of writing under the
address 0xFF04 – 0xFF07. Polarization of the pulse is set by the SEL1POL
bit.
1
01
Read strobe.
A pulse is generated at the moment of reading under the
address 0xFF04 – 0xFF07. Polarization of the pulse is set by the SEL1POL
bit.
2
10
Address decoder.
A pulse is generated at the moment of writing or reading
from the address 0xFF04-0xFF07. Polarization of the pulse is set by the
SEL1POL bit.
3
11
Additional output.
Signal SEL1 assumes the value of the SEL1POL bit.