17
Mode SEL2CFG1..0
Description
0
00
Write strobe.
A pulse is generated at the moment of writing under the
address 0xFF08 – 0xFF0B. Pulse polarization is set by the SEL2POL bit.
1
01
Read strobe.
A pulse is generated at the moment of reading under the
address 0xFF08 – 0xFF0B. Pulse polarization is set by the SEL2POL bit.
2
10
Address decoder.
A pulse is generated at the moment of writing or reading
under the address 0xFF08 – 0xFF0B. Pulse polarization is set by the
SEL2POL bit.
3
11
If the module is fitted with a 256kB of RAM memory, output SEL2 is used as
the highest bit of the address bus (in this case it must operate in mode 3)
and cannot be used outside the module. If the module is fitted with a 128kB
of RAM memory, output SEL2 in mode 3 can be used as additional output.
It takes then the state of bit 3 in the MMnet102_BANKSR register.
The drawings below illustrate the operation of output SEL during writing or reading operation.
0xFF04-0xFF07 - SEL1
x
x
SELx
#WR
#RD
ADDR
0xFF08-0xFF0B - SEL2
Figure 3
Operation of SEL output as write strobe (SELxCFG1..0=00) with active low level (SELxPOL = 0).
x
x
SELx
#WR
#RD
ADDR
0xFF04-0xFF07 - SEL1
0xFF08-0xFF0B - SEL2
Figure 4
Operation of SEL output as write strobe (SELxCFG1..0=00) with active high level (SELxPOL = 1).
