14
Memory controller
The memory controller, built around the CPLD programmable device, controls the address space of the
microcontroller, generates address strobe/selection signals to be exploited by the user and serves in banking
of the RAM memory.
The memory controller can operate in three modes which differ in the placement of areas in the address
space:
•
Mode of conformity with the EVBedu.net and Ethernet 1 boards – only 32kB of RAM memory is
available, situated in the range to 0x7FFF. The registers of the LAN91C111 circuit are under the
addresses: 0x8000 – 0x9000. The rest of the RAM memory is not accessible.
•
Memory banking mode. In order to exploit fully the whole memory, the address decoder facilitates the
division of the memory into banks of 16kB each. In the range until 0x7FFF the basic unbanked
memory is located. Under the addresses 0x8000 – 0xBFFF is the currently used memory bank. The
choice of a bank is effected by writing its number to the bank register which is located under the
address 0xFF00. In the location up to 0x7FFF (basic memory) always the last bank is visible. Such a
solution is always favorable when programming is done in C language, as environment variables and
buffers, often used in the program, can be held in the basic memory, while the space with the variable
bank number can be used e.g. to collect measurement data, large tables or buffers, the access to
which is not hampered by a change in bank number. The Ethernet controller is under the address
0xC000.
•
Maximum linear memory mode – the Ethernet controller is at the end of the address space under the
address 0xFF80. The linear memory reaches the address 0xFEFF. This mode permits the
achievement of a large linearly addressed memory of the size of 65280B.
The memory controller allows also the generation of two signals: SEL1 and SEL2. These signals can be
configured as write/read strobe lines or address choice with any polarization. The configuration is achieved by
means of appropriate registers.
The address space of the microcontroller under the addresses 0xFF00 to 0xFFFF contains an area reserved
for MMnet102. It has two registers: a configuration and bank select registers, an area for the peripherals
controlled by the SEL outputs and an area for the Ethernet controller.
This is depicted in the picture below:
…
FF80 – FF9F
LAN91C111
Ethernet ctrl registers
…
FF08 – FF0B
MMnet102_SEL2
External I/O
FF04 – FF07
MMnet102_SEL1
External I/O
…
FF01
MMnet102_CONF
Configuration register
FF00
MMnet102_BANKSR
Bank select register
