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PEX 8632-AA Quick Start

Hardware Design Guide

Version 1.1

October, 2007

Website:

www.plxtech.com

Support:

www.plxtech.com/support

Phone:

800 759-3735
408 774-9060

Fax:

408 774-2169

Содержание PEX 8632-AA

Страница 1: ...PEX 8632 AA Quick Start Hardware Design Guide Version 1 1 October 2007 Website www plxtech com Support www plxtech com support Phone 800 759 3735 408 774 9060 Fax 408 774 2169...

Страница 2: ...me without notice Products may have minor variations to this publication known as errata PLX assumes no liability whatsoever including infringement of any patent or copyright for sale and use of PLX p...

Страница 3: ...6 PCI Express Port Good Indicators 12 1 6 1 PCI Express Port Good Indicators 8 Port Mode 12 1 6 2 PCI Express Port Good Indicators 12 Port Mode 12 1 7 Strapping Balls 13 1 7 1 Strapping Balls 8 Port...

Страница 4: ...r Plane Impedance versus Frequency 19 Figure 13 Capacitor Footprint Effects on Series Inductance 20 Figure 14 Top Layer BGA Layout and Routing Escape 22 Figure 15 Bottom Layer BGA Layout Escape and De...

Страница 5: ...this document is subject to change without notice Although every effort has been made to ensure the accuracy of this manual PLX shall not be liable for any errors incidental or consequential damages i...

Страница 7: ...s examples of how to connect to the various switch interfaces 1 Switch Interfaces The PEX 8632 device is a 32 Lane 8 or 12 Port Gen2 switch designed for high availability and high performance systems...

Страница 8: ...Link is described in terms of four components Transmitter Receiver Reference Clock and Channel The Transmitter and Receiver elements are typically integrated into PCI Express silicon The Channel and...

Страница 9: ...es De emphasis does this by reducing the amount of energy used to transmit multiple successive bits of the same polarity that is non transition bits compared to the amount of energy used to transmit a...

Страница 10: ...de emphasis ratio The PLX driver is implemented as a two tap driver When transition bits are transmitted the SerDes Drive Level and Post Cursor Emphasis Level register levels are added together for no...

Страница 11: ...s base clock Jitter on the base CDR clock and or the incoming data stream can cause bit sampling errors to occur Although not explicitly mentioned in the PCI Express Base Specification Revision 2 0 Re...

Страница 12: ...y jitter including Spread Spectrum Clock SSC modulation is tracked by the CDR circuit whereas higher frequency jitter content causes eye closure at the Receiver The cut off frequency of the CDR high p...

Страница 13: ...low pass filter due to frequency dependent dielectric and conductor losses In PCI Express the Channel contributes to amplitude loss and deterministic jitter It is important to minimize discontinuitie...

Страница 14: ...elect Port 0 1 2 or 3 as the NT Port at Station 0 Method 2 Enable the NT function and configure the NT Port through the serial EEPROM when the PEX 8632 switch is powered up Method 3 Use the PEX 8632 I...

Страница 15: ...ble Ports 1 5 and 9 respectively As long as the related Port is used the PHPC functions normally Otherwise the PHPC is disabled Each PHPC has 10 Hot Plug signal balls for controlling various Hot Plug...

Страница 16: ...2 locates the I O expander IC it automatically assigns a valid Port Number for this SHPC Figure 8 illustrates a block diagram of the SHPC interface to the PEX 8632 The SHPC has more signals than the P...

Страница 17: ...to 2 5V with 1 to 5 kohm resistors Pull JTAG_TRST down to VSS with a 1 to 5 kohm resistor Because the PEX 8632 JTAG clock frequency can be as high as 25 MHz a 15 ohm series terminator can be added to...

Страница 18: ...Table 2 lists the relationship of the LED On Off patterns to the Port status Table 2 PEX 8632 LED On Off Patterns by State State LED Pattern Link is down Off Link is up 5 GT s all Lanes are up On Link...

Страница 19: ...e STRAP_RESERVED balls have their own pull up and pull down resistor requirements Table 3 lists the names and functions of the PEX 8632 Configuration Strapping balls Table 4 lists which Lanes are acti...

Страница 20: ...X X X X X X X X X X X X X 12 Port Mode X X X X X X X X X X X X Lane 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 8 Port Mode 12 Port Mode X X X X X X X X Table 5 STRAP_RESERVED Ball External Pull...

Страница 21: ...r own pull up and pull down resistor requirements Table 6 lists the names and functions of the PEX 8632 Configuration Strapping balls Table 4 on page 14 lists which Lanes are active depending upon whe...

Страница 22: ...share GPIO and PEX_PORT_GOOD 7 0 functions in standard operation Depending upon the settings of the Test mode balls STRAP_TESTMODE 3 0 the GPIO balls can be set as input output and or bidirectional Ei...

Страница 23: ...plane The current demands for these supplies can be high depending upon the device approximately 80 mA per Lane plus 32 mA therefore ensure that the power plane is sufficiently sized to support the s...

Страница 24: ...pacitance for the VDD25 rail VDD25A and VSSA_PLL are used to power the internal Reference Clock PLL This ball might require additional filtering circuitry if the VDD25 plane is experiencing significan...

Страница 25: ...capacitors can typically be effective for frequencies up to 250 MHz For frequency components higher than 250 MHz plane capacitance provides the only effective means for de coupling Figure 12 illustrat...

Страница 26: ...placement of small discrete capacitors is not critical Place the capacitors on the solder side of the board under the Ball Grid Array BGA footprint in the solder ball void area and directly outside t...

Страница 27: ...on the outer two rows of balls and Receiver differential pairs on rows three and four This means it should take two signal layers in a PCB layer stackup to escape the differential pairs from the BGA A...

Страница 28: ...yer BGA Layout and Routing Escape Figure 15 Bottom Layer BGA Layout Escape and De coupling Capacitor Placement PEX 8632 AA Quick Start Hardware Design Guide Version 1 1 22 2007 PLX Technology Inc All...

Страница 29: ...Either location should have plenty of ground vias PCI Express add in boards must be length matched within 5 mil AC coupling capacitors should be placed close to the gold fingers Differential pairs for...

Страница 30: ...l signals the last step is to determine the separation between the positive and negative conductors to achieve the needed differential impedance Additionally a PCB layer stackup can determine the powe...

Страница 31: ...8632 AA Data Book Version 0 60 or higher PCI Special Interest Group PCI SIG 3855 SW 153rd Drive Beaverton OR 97006 USA Tel 503 619 0569 Fax 503 644 6708 www pcisig com PCI Local Bus Specification Revi...

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