PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1
4
© 2007 PLX Technology, Inc. All Rights Reserved.
In addition to supporting the standard de-emphasis levels, the PEX 8632 has a number of programmable
registers to control the Transmitter’s characteristics,
such as
drive level and de-emphasis.
8-Port mode
– The SerDes Transmitter Control registers exist in Station Ports 0 and 4, each
controlling a bank of 16 SerDes (Lanes [0-15] and [16-31], respectively).
12-Port mode
– The SerDes Transmitter Control registers exist in Station Ports 0, 4, and 8.
Ports 0 and 4 each control a bank of 12 SerDes (Port 0 – Lanes [0-9, 12, 13]; Port 4 –
Lanes [16-25, 28, 29]). Port 8 controls a bank of 10 SerDes (Lanes [32, 33, 36, 37, 40, 41,
44, 45]).
Registers at offsets B84h to B90h are the
SerDes Drive Level
registers. Registers at offsets B94h to
BA0h are the
Post-Cursor Emphasis Level
registers. The
SerDes Drive Level
and
Post-Cursor
Emphasis Level
registers work in conjunction, to determine the transition and non-transition bits driver
swing and de-emphasis ratio. The PLX driver is implemented as a two-tap driver. When transition bits are
transmitted, the
SerDes Drive Level
and
Post-Cursor Emphasis Level
register levels are added
together; for non-transition bits, the two values are subtracted. Using
presents a
calculation of what the drive level and de-emphasis level would be for a given set of register values.
Systems with short Links and/or power-sensitive applications (
such as
mobile platforms) can optionally
decide to use low-swing output drive levels (40 0 mV
P-P
). In the PEX 8632, this can be accomplished by
setting the
SerDes Drive Level
register for a specific Lane to 01000b (400 mV
P-P
), and the
Post-Cursor
Emphasis Level
register to 00000b (no de-emphasis).
Equation 1. PEX 8632 Transmitter Drive Level
(a) V
TRANS
= V
DRV_LVL
+ V
POST_EMP
(b) V
NON-TRANS
= V
DRV_LVL
- V
POST_EMP
(c) V
TX-DE-RATIO-3.5DB
= 20 log (V
POST_EMP
/ V
DRV_LVL
)
Example 1. Setting for Lane 0 Transmitter to 3.5 dB
Port 0
SerDes Drive Level
register, offset B84h[4:0] = 01111b (750 mVpp)
Port 0
Post-Cursor Emphasis
Level
register, offset B94h[4:0] = 01101b (162.5 mVpp)
V
TRANS
= 750 mV + 162.5 mV = 912.5 mVpp
V
NON-TRANS
=
750 mV - 162.5 mV = 587.5 mVpp
V
TX-DE-RATIO-3.5 DB
= 20 log (587.5/912.5) = -3.82 dB
