PLX Technology PEX 8632-AA, Быстрый старт

Страница: 17 / 31

1.4 JTAG Interface
The PEX 8632 supports a five-ball JTAG Boundary Scan interface. The JTAG interface consists of the
following signals:
ƒ
JTAG_TCK
ƒ
JTAG_TDI
ƒ
JTAG_TDO
ƒ
JTAG_TMS
ƒ
JTAG_TRST#
At the board level, pull JTAG_TCK, JTAG_TDI, and JTAG_TMS up to 2.5V with 1- to 5-kohm resistors.
Pull JTAG_TRST# down to VSS with a 1- to 5-kohm resistor. Because the PEX 8632 JTAG clock
frequency can be as high as 25 MHz, a 15-ohm series terminator can be added to TCK, TDI, and TDO, to
improve signal quality.
Figure 9 illustrates a generic JTAG interconnection.
Figure 9. JTAG Interface Block Diagram
PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1
© 2007 PLX Technology, Inc. All Rights Reserved.
11