Pioneer VSX-817-K, Руководство по обслуживанию

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VSX-917V-K
127
5 6 7 8
5 6
7
8
C
D
F
A
B
E
Pin Arrangement (Top view)
Pin Description
Block Diagram
1
2
3
4
CS#
SO
WP#
VSS
VDD
HOLD#
SCK
SI
8
7
6
5
ADDRESS
BUFFERS
&
LATCHES
X-
DECODER
1M bit
Flash EEPROM
Cell Array
Y-DECODER
I/O BUFFERS
&
DATA LATCHES
CONTROL
LOGIC
SERIAL INTERFACE
CS# SCK
SCK Serial clock
To control the timing of serial data input and output.
To latch input data and addresses synchronously at the rising edge of SCK, and
read out Output data synchronously at the falling edge.
Serial data input To input data or addresses serially from MSB to LSB (Least Significant Bit).
To output data serially from MSB to LSB.
To write-protect the Block Protect bits (BP0, BP1) and the Status Register Write
Protect bit (SRWP) of the Status Register in co-operation with the Status Register
Write Protect bit (SRWP).
To activate the device when this pin is LOW.
To deselect and put the device to standby mode when this pin is HIGH.
Serial data input
Chip select
Write-protect
Hold To pause any serial communications with the device without deselecting the device.
To provide from 2.7V to 3.6V supply Power supply
Ground
CS#
WP#
HOLD#
VDD
VSS
SI
SO
Symbol Pin Description Function
SI SO WP# HOLD#
7
PDC151A8 (DSP ASSY : IC851)
• FLASH ROM