209
MEP-7000
5
6
7
8
5
6
7
8
A
B
C
D
E
F
3
8
37
36
FPGA_MCLK
N
o.(SCH/PCB)
CH1
FPGA_MCLK
9
FPGA_MCLK (TP)
CH1
HUB_24MHz
N
o.(SCH/PCB)
CH1
HUB_24M
15
HUB_24M (TP)
CH1
USB_6MHz
N
o.(SCH/PCB)
CH1
USB_6M
14
USB_6M (TP)
CH1
1.0V/div
1.0V/div
20ns/div
50ns/div
1.0V/div
20ns/div
CH1
USB_6M
CH1
HUB_24M
CH1
FPGA_MCLK
G
N
D
G
N
D
G
N
D
Measurement conditions
Voltage
Time
Signal
N
ame
Measurement Point
Idling
Measurement conditions
Voltage
Time
Signal
N
ame
Measurement Point
Idling
Measurement conditions
Voltage
Time
Signal
N
ame
Measurement Point
Idling