Pioneer DVJ-1000, Руководство по обслуживанию

Страница: 154 / 160

DVJ-1000
154
1 2 3 4
1 2 3 4
C
D
F
A
B
E
HD6417709SHF200B (MAIN ASSY : IC111) (2/3) [CPU]
Pin Function
No. Pin name Signal name I/O Function
74 A17 A17 O Address bus
75 A18 A18 O Address bus
76 A19 A19 O Address bus
77 A20 A20 O Address bus
78 A21 A21 O Address bus
79 Vss GNDD - Power supply (0V)
80 A22 A22 O Address bus
81 Vcc V+2SH - Power supply (2.0V)
82 A23 A23 O Address bus
83 VssQ GNDD - Power supply for input/output (0V)
84 A24 A24 O Address bus
85 VccQ V+3SH - Power supply for input/output (3.3V)
86 A25 A25 O Address bus
87 XBS XBS O/IO Bus cycle start signal
88 XRD RD O Read strobe
89 XWE0 XWE0 O Write strobe
90 XWE1 XWE1 O Write strobe
91 XWE2 XWE2 O/IO Write strobe
92 XWE3 XWE3 O/IO Write strobe
93 RDXWR RDWR O Read/write
94 XAUDSYNC AUDSYNC - -
95 VssQ GNDD - Power supply for input/output (0V)
96 XCS0 XCS0 O CS0
97 VccQ V+3SH - Power supply for input/output (3.3V)
98 XCS2 XCS2 O/IO CS2
99 XCS3 XCS3 O/IO CS3 (for SDRAM)
100 XCS4 XCS4 O/IO CS4
101 XCS5 XCS5 O/IO CS5
102 XCS6 XCS6 O CS6
103 PTE[4] P_XI O/IO Progressive/interlace switching
104 PTE[5] PRO2_XCS O/IO Chip select output for PM0033A
105 CKE CKE O/IO CKE(SDRAM)
106 XRAS3L RAS3L O/IO RAS3L(SDRAM)
107 PTJ[1] AV1_RST O AV-1 reset
108 XCASL CASL O/IO CASL(SDRAM)
109 VssQ GNDD - Power supply for input/output (0V)
110 PTJ[3] MOT_RST O Reset for Motorola DSP
111 VccQ V+3SH - Power supply for input/output (3.3V)
112 PTJ[4] TI_RST O Reset for TI DSP
113 PTJ[5] VDEC_RST O Reset for MPEG decoder
114 XDACK0 XDACK0 O DMA acknowledge 0
115 XDACK1 XDACK1 O DMA acknowledge 1
116 PTE[6] AQE_RST O PD0274A reset
117 PTE[3] - - -
118 XRAS3U 44X48 O/IO 44.1/48K selection
119 PTE[1] MUTE O/IO Audio output stage mute (mute ON at H)
120 TDO TDO - -
121 XBACK BACK O -
122 XBREQ BREQ I pull up
123 XWAIT XWAIT I Connect to FPGA
124 XRESETM RESETM I pull up
125 XADTRG FPGA_DONE I DONE for FPGA configuration
126 XIOIS16 RY/XBY I Connection to FLASH ROM
127 XASEMD0 ASEMD0 - -
128 XASEBRKAK ASEBRKAK - -
129 PTG[4] FPGA_XINIT I INIT for FPGA configuration
130 AUDATA[3] AUDATA[3] - -
131 AUDATA[2] AUDATA[2] - -
132 Vss GNDD - Power supply (0V)
133 AUDATA[1] AUDATA[1] - -
134 Vcc V+2SH - Power supply (2.0V)
135 AUDATA[0] AUDATA[0] - -
136 XTRST TRST - -
137 TMS TMS - -
138 TDI TDI - -
139 TCK TCK - -
140 PINT[11] VDEC_XINT I MPEG2 decoder interrupt
141 PINT[10] AV1_XINTR I PINT[10] AV-1 INTR interrupt
142 PINT[9] GSL_XIRQS I PIN[9] GSL XIRQS interrupt
143 PINT[8] GSL_XIRQ I PIN[8] GSL XIRQ interrupt
144 MD0 MD0 I pull up
145 Vcc-PLL1 V+2SH - Power supply for PLL1 (2.0V)
146 CAP1 CAP1 - C