DV-59AVi
139
5
6
7
8
5
6
7
8
C
D
F
A
B
E
Pin No.
Mnemonic
Input/Output
Function
50
S_HSYNC
I/O
Video Horizontal Sync Control Signal for SD Only.
49
S_VSYNC
I/O
Video Vertical Sync Control Signal for SD Only.
2–9, 12–13
Y9–Y0
I
SD or Progressive Scan/HDTV Input Port for Y Data. Input port for inter-
leaved progressive scan data. The LSB is set up on Pin Y0. For 8-bit data
input, LSB is set up on Y2.
14–18, 26–30 C9–C0
I
Progressive Scan/HDTV Input Port. In 4:4:4 Input mode, this port is used for
the Cb[Blue/U] data. The LSB is set up on Pin C0. For 8-bit data input, LSB
is set up on C2.
51–55, 58–62 S9–S0
I
SD or Progressive Scan/HDTV Input Port for Cr [Red/V] Data in 4:4:4 Input
Mode. LSB is set up on Pin S0. For 8-bit data input, LSB is set up on S2.
33
RESET
I
This input resets the on-chip timing generator and sets the ADV7314 into
default register setting. RESET is an active low signal.
35, 47
R
SET2
, R
SET1
I
A 3040
Ω
resistor must be connected from this pin to AGND and is used
to control the amplitudes of the DAC outputs.
22
SCLK
I
I
2
C Port Serial Interface Clock Input.
21
SDA
I/O
I
2
C Port Serial Data Input/Output.
20
ALSB
I
TTL Address Input. This signal sets up the LSB of the I
2
C address. When
this pin is tied low, the I
2
C filter is activated, reducing noise on the I
2
C
interface.
1
V
DD_IO
P
10, 56
V
DD
P
Digital Power Supply.
41
V
AA
P
Analog Power Supply.
46
V
REF
I/O
Optional External Voltage Reference Input for DACs or Voltage Reference
Output (1.235 V).
34
EXT_LF
I
External Loop Filter for the Internal PLL.
31
RTC_SCR_TR
I
I
M ultifunctional Input. Real-time control (RTC) input, timing reset input,
subcarrier reset input.
19
I
2
C
This input pin must be tied high (V
DD_IO
) for the ADV7314 to interface
over the I
2
C port.
64
GND_IO
Digital Input/Output Ground.
TERMINOLOGY
SD
Standard definition video, conforming to ITU-R BT.601/656.
HD
High definition video, such as progressive scan or HDTV.
PS
Progressive scan video, conforming to SMPTE 293M, ITU-R BT.1358, BTA T-1004 EDTV2, BTA 1362
HDTV
High definition television video, conforming to SMPTE 274M or SMPTE 296M.
YCrCb
SD, HD, or PS component digital video.
YPrPb
HD, SD, or PS component analog video.
Power Supply for Digital Inputs and Outputs.
Содержание DV-59AVi
Страница 13: ...DV 59AVi 13 5 6 7 8 5 6 7 8 C D F A B E ...
Страница 52: ...DV 59AVi 52 1 2 3 4 1 2 3 4 C D F A B E ...
Страница 118: ...DV 59AVi 118 1 2 3 4 1 2 3 4 C D F A B E 7 M65776BFP DVDM ASSY IC751 MPEG2 Decorder IC Block Diagram ...
Страница 123: ...DV 59AVi 123 5 6 7 8 5 6 7 8 C D F A B E 7 LA73054 VJKB ASSY IC302 IC601 DVD Video Amplifier Block Diagram ...
Страница 125: ...DV 59AVi 125 5 6 7 8 5 6 7 8 C D F A B E 7 CXD2753R DVDM ASSY IC1110 SACD Decorder Pin Arrangement ...
Страница 140: ...DV 59AVi 140 1 2 3 4 1 2 3 4 C D F A B E 7 ADV7310KST DVDM ASSY IC903 Video Encoder IC Pin Arrangement ...
Страница 142: ...DV 59AVi 142 1 2 3 4 1 2 3 4 C D F A B E 7 TSB43CA42GGW DVDM ASSY IC801 IEEE1394 PHY LINK Pin Arrangement ...
Страница 169: ...DV 59AVi 169 5 6 7 8 5 6 7 8 C D F A B E ...