Pioneer DV-59AVi, Руководство по обслуживанию

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DV-59AVi
159
5 6 7 8
5 6
7
8
C
D
F
A
B
E
No. Name I/O Function
97 MA9 O SDRAM address output terminal
98 OVDD
−
VDD (3.3 V) for I/O
99 OVSS
−
Digital GND
100 RAS O SDRAM "Row Address Strobe" command output terminal
101 DQM O
SDRAM DQM output terminal. The CKE terminal of the SDRAM must be connected to the power
source for the SDRAM.
102 CAS O SDRAM "Column Address Strobe" command output terminal
103 MCLK O SDRAM clock output terminal (54 MHz)
104 WE O SDRAM "Write Enable" command output terminal
105 TEST3 I Input terminal dedicated for testing. To be connected to ground.
106 TEST4 I Input terminal dedicated for testing. To be connected to ground.
107 OVSS
−
Digital GND
108 OVDD
−
VDD (3.3 V) for I/O
109 CVDD
−
VDD (2.5 V) for the core
110 MD7 I/O SDRAM data input/output terminal
111 MD8 I/O SDRAM data input/output terminal
112 MD6 I/O SDRAM data input/output terminal
113 MD9 I/O SDRAM data input/output terminal
114 OVDD
−
VDD (3.3 V) for I/O
115 OVSS
−
Digital GND
116 MD5 I/O SDRAM data input/output terminal
117 MD10 I/O SDRAM data input/output terminal
118 MD4 I/O SDRAM data input/output terminal
119 MD11 I/O SDRAM data input/output terminal
120 OVDD
−
VDD (3.3 V) for I/O
121 OVSS
−
Digital GND
122 MD3 I/O SDRAM data input/output terminal
123 MD12 I/O SDRAM data input/output terminal
124 MD2 I/O SDRAM data input/output terminal
125 MD13 I/O SDRAM data input/output terminal
126 OVSS
−
Digital GND
127 CVSS
−
Digital GND
128 OVDD
−
VDD (3.3 V) for I/O
129 MD1 I/O SDRAM data input/output terminal
130 MD14 I/O SDRAM data input/output terminal
131 MD0 I/O SDRAM data input/output terminal
132 MD15 I/O SDRAM data input/output terminal
133 SLV I MPU Interface slave address setting input terminal
134 RFFO O MPEG data (repeat_first_field flag) output terminal. When not in use, make it open.
135 SDA I/O MPU Interface data input/output terminal
136 SCL I MPU Interface clock input terminal
137 SRN I System reset input terminal
138 OVSS
−
Digital GND
139 CVDD
−
VDD (2.5 V) for the core
140 PLL_VDD
−
VDD (2.5 V) dedicated for PLL
141 VPDX I To be connected to ground
142 TEST6 I Input terminal dedicated for testing. To be connected to ground.
143 PLL_GND
−
GND dedicated for PLL
144 IVDD
−
VDD (3.3 V) for I/O