DJM-1000
152
1
2
3
4
1
2
3
4
C
D
F
A
B
E
No.
Pin Name
I/O
Pin Function
MULTICHANNEL AUDIO SERIAL PORT 1 (McASP1) (CONTINUED)
146
HCNTL0/AXR0[12]/AXR1[3]
I/O/Z
Host control - selects between control, address, or data registers (I) [default] or McASP0 TX/RX
data pin 12 (I/O/Z) or McASP1 TX/RX data pin 3 (I/O/Z).
145
HCS/AXR0[13]/AXR1[2]
I/O/Z
Host chip select (I) [default] or McASP0 TX/RX data pin 13 (I/O/Z) or McASP1 TX/RX data pin 2
(I/O/Z).
144
HCNTL1/AXR0[14]/AXR1[1]
I/O/Z
Host control - selects between control, address, or data registers (I) [default] or McASP0 TX/RX
data pin 14 (I/O/Z) or McASP1 TX/RX data pin 1 (I/O/Z).
143
HR/W/AXR0[15]/AXR1[0]
I/O/Z
Host read or write select (I) [default] or McASP1 TX/RX data pin 0 (I/O/Z) or McASP0 TX/RX
data pin 15 (I/O/Z).
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0)
6
GP0[5](EXT_INT5)/AMUTEIN0
I/O/Z General-purpose input/output 0 pin 5 and external interrupt 5 (I/O/Z) [default] or McASP0 mute input (I/O/Z).
33
CLKX1/AMUTE0
I/O/Z McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (O/Z).
19
CLKR0/ACLKR0
I/O/Z McBSP0 receive clock (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z).
12
TINP1/AHCLKX0
I/O/Z Timer 1 input (I) [default] or McBSP0 transmit high-frequency master clock (I/O/Z).
16
CLKX0/ACLKX0
I/O/Z McBSP0 transmit clock (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z).
28
CLKS0/AHCLKR0
I/O/Z
McBSP0 external clock source (as opposed to internal) (I) [default] or McASP0 receive high-
frequency master clock (I/O/Z).
24
FSR0/AFSR0
I/O/Z
McBSP0 receive frame sync (I/O/Z) [default] or McASP0 receive frame sync or left/right clock
(LRCLK) (I/O/Z).
21
FSX0/AFSX0
I/O/Z
McBSP0 transmit frame sync (I/O/Z) [default] or McASP0 transmit frame sync or left/right clock
(LRCLK) (I/O/Z).
27
DR0/AXR0[0]/AXR1[15]
I/O/Z
McBSP0 receive data (I) [default] or McASP0 TX/RX data pin 0 (I/O/Z) or McASP1 TX/RX data
pin 15 (I/O/Z).
20
DX0/AXR0[1]/AXR1[14]
I/O/Z
McBSP0 transmit data (O/Z) [default] or McASP0 TX/RX data pin 1 (I/O/Z) or McASP1 TX/RX
data pin 14 (I/O/Z).
18
TOUT0/AXR0[2]/AXR1[13]
I/O/Z Timer 0 output (O) [default] or McASP0 TX/RX data pin 2 (I/O/Z) or McASP1 TX/RX data pin 13
(I/O/Z).
17
TINP0/AXR0[3]/AXR1[12]
I/O/Z
Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z) or McASP1 TX/RX data pin 12
(I/O/Z).
13
TOUT1/AXR0[4]/AXR1[11]
I/O/Z
Timer 1 output (O) [default] or McASP0 TX/RX data pin 4 (I/O/Z) or McASP1 TX/RX data pin 11
(I/O/Z).
32
DX1/AXR0[5]/AXR1[10]
I/O/Z
McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z) or McASP1 TX/RX
data pin 10 (I/O/Z).
36
CLKR1/AXR0[6]/AXR1[9]
I/O/Z
McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z) or McASP1 TX/RX
data pin 9 (I/O/Z).
38
FSR1/AXR0[7]/AXR1[8]
I/O/Z
McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7 (I/O/Z) or McASP1
TX/RX data pin 8 (I/O/Z).
152
HD1/AXR0[8]/AXR1[7]
I/O/Z
Host-port data pin 1 (I/O/Z) [ default] or McASP0 TX/RX data pin 8 (I/O/Z) or McASP1 TX/RX
data pin 7 (I/O/Z).
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) (CONTINUED)
151
HDS1/AXR0[9]/AXR1[6]
I/O/Z
Host data strobe 1 (I) [default] or McASP0 TX/RX data pin 9 (I/O/Z) or McASP1 TX/RX data pin
6 (I/O/Z).
150
HDS2/AXR0[10]/AXR1[5]
I/O/Z
Host data strobe 2 (I) [default] or McASP0 TX/RX data pin 10 (I/O/Z) or McASP1 TX/RX data
pin 5 (I/O/Z).
147
HD0/AXR0[11]/AXR1[4]
I/O/Z
Host-port data pin 0 (I/O/Z) [ default] or McASP0 TX/RX data pin 11 (I/O/Z) or McASP1 TX/RX
data pin 4 (I/O/Z).
146
HCNTL0/AXR0[12]/AXR1[3]
I/O/Z
Host control - selects between control, address, or data registers (I) [default] or McASP0 TX/RX
data pin 12 (I/O/Z) or McASP1 TX/RX data pin 3 (I/O/Z).
145
HCS/AXR0[13]/AXR1[2]
I/O/Z
Host chip select (I) [default] or McASP0 TX/RX data pin 13 (I/O/Z) or McASP1 TX/RX data pin 2
(I/O/Z).
144
HCNTL1/AXR0[14]/AXR1[1]
I/O/Z
Host control - selects between control, address, or data registers (I) [default] or McASP0 TX/RX
data pin 14 (I/O/Z) or McASP1 TX/RX data pin 1 (I/O/Z).
143
HR/W/AXR0[15]/AXR1[0]
I/O/Z
Host read or write select (I) [default] or McASP0 TX/RX data pin 15 (I/O/Z) or McASP1 TX/RX
data pin 0 (I/O/Z).
Содержание DJM-1000
Страница 13: ...DJM 1000 13 5 6 7 8 5 6 7 8 C D F A B E ...
Страница 21: ...DJM 1000 21 5 6 7 8 5 6 7 8 C D F A B E A 2 4 1 4 A FROM FROM ...
Страница 43: ...DJM 1000 43 5 6 7 8 5 6 7 8 C D F A B E CN4 A 4 4 L VISUAL MIDI TX SELECTOR ...
Страница 48: ...DJM 1000 48 1 2 3 4 1 2 3 4 C D F A B E 3 19 PANEL1 ASSY CN202 A 1 4 CN4013 S CN4010 S P PANEL1 ASSY DWX2427 P ...
Страница 49: ...DJM 1000 49 5 6 7 8 5 6 7 8 C D F A B E CN4012 S CN901 T CN902 W P ...
Страница 50: ...DJM 1000 50 1 2 3 4 1 2 3 4 C D F A B E 3 20 PANEL2 and ISOLATOR ASSYS Q R ISOLATOR ASSY DWX2425 R ...
Страница 51: ...DJM 1000 51 5 6 7 8 5 6 7 8 C D F A B E Q CN4002 S CN4001 S CN907 M PANEL2 ASSY DWX2428 Q ...
Страница 168: ...DJM 1000 168 1 2 3 4 1 2 3 4 C D F A B E Jigs list Jig No Jig Name Remarks GGF1490 RS 232C jig used for version up mode ...