Pioneer DJM-1000, Руководство по обслуживанию

Страница: 149 / 168

DJM-1000
149
5 6 7 8
5 6
7
8
C
D
F
A
B
E
No. Pin Name I/O Pin Function
CLOCK/PLL CONFIGURATION
204 CLKIN I Clock Input
82 CLKOUT2/GP0[2] O/Z
Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal from the PLL
controller) or this pin can be programmed as GP0[2] pin (I/O/Z)
184 CLKOUT3 O Programmable clock output (OSC Divider internal signal from PLL controller)
205 CLKMODE0 I PLL input clock source select
202 PLLHV A Analog power (3.3 V) for PLL
178 OSCIN I Crystal oscillator Input (XI)
179 OSCOUT O Crystal oscillator output (XO)
181 OSCVDD S Power supply for crystal oscillator (1.2 V)
180 OSCVSS GND Ground for crystal oscillator
JTAG EMULATION
192 TMS I JTAG test-port mode select
187 TDO O/Z JTAG test-port data output
191 TDI I JTAG test-port data input
193 TCK I JTAG test-port clock
197 TRST I JTAG test-port reset
185 EMU1 I/O/Z
Emulation [1:0] pin
186 EMU0 I/O/Z
RESETS AND INTERRUPTS
176 RESET I Device reset
175 NMI I Nonmaskable interrupt
7 GP0[7](EXT_INT7) I/O/Z General-purpose input/output 0 pins (I/O/Z) which also function as external interrupts [default]
• Edge driven • Polarity independently selected via the External Interrupt Polarity Register bits
(EXTPOL.[3:0]) GP0[4] and GP0[5] pins also function as AMUTEIN1 McASP1 mute input and
AMUTEIN0 McASP0 mute input, respectively.
2 GP0[6](EXT_INT6) I/O/Z
6
GP0[5](EXT_INT5)/AMUTEIN0
I/O/Z
1
GP0[4](EXT_INT4)/AMUTEIN1
I/O/Z
HOST-PORT INTERFACE (HPI)
174 HD15/GP0[15] I/O/Z
Host-port data pins (I/O/Z) [default] or general-purpose input/output 0 pins (I/O/Z) and some
function as boot configuration pins at reset.
173 HD14/GP0[14] I/O/Z
172 HD13/GP0[13] I/O/Z
168 HD12/GP0[12] I/O/Z
167 HD11/GP0[11] I/O/Z
166 HD10/GP0[10] I/O/Z
165 HD9/GP0[9] I/O/Z
160 HD8/GP0[8] I/O/Z
164 HD7/GP0[3] I/O/Z
HOST-PORT INTERFACE (HPI) (CONTINUED)
161 HD6/AHCLKR1 I/O/Z Host-port data pin 6 (I/O/Z) [ default] or McASP1 receive high-frequency master clock (I/O/Z).
159 HD5/AHCLKX1 I/O/Z Host-port data pin 5 (I/O/Z) [ default] or McASP1 transmit high-frequency master clock (I/O/Z).
156 HD4/GP0[0] I/O/Z
Host-port data pin 4 (I/O/Z) [ default] or this pin can be programmed as a GP0 0 pin (I/O/Z) and
is external interrupt capable through interrupt sharing.
154 HD3/AMUTE1 I/O/Z Host-port data pin 3 (I/O/Z) [ default] or McASP1 mute output (O/Z).
155 HD2/AFSX1 I/O/Z Host-port data pin 2 (I/O/Z) [ default] or McASP1 transmit frame sync or left/right clock (LRCLK) (I/O/Z).
152 HD1/AXR0[8]/AXR1[7] I/O/Z
Host-port data pin 1 (I/O/Z) [ default] or McASP0 TX/RX pin 8 (I/O/Z) or McASP1 TX/RX pin 7
(I/O/Z).
147 HD0/AXR0[11]/AXR1[4] I/O/Z
Host-port data pin 0 (I/O/Z) [ default] or McASP0 TX/RX pin 11 (I/O/Z) or McASP1 TX/RX pin 4
(I/O/Z).
135 HINT/GP0[1] O/Z
Host interrupt (from DSP to host) (O) [default] or this pin can be programmed as a GP0 1 pin (I/O/Z).
144 HCNTL1/AXR0[14]/AXR1[1] I
Host control - selects between control, address, or data registers (I) [default] or McASP0 TX/RX
pin 14 (I/O/Z) or McASP1 TX/RX pin 1 (I/O/Z).
146 HCNTL0/AXR0[12]/AXR1[3] I
Host control - selects between control, address, or data registers (I) [default] or McASP0 TX/RX
pin 12 (I/O/Z) or McASP1 TX/RX pin 3 (I/O/Z).
139 HHWIL/AFSR1 I
Host half-word select - first or second half-word (not necessarily high or low order) (I) [default] or
McASP1 receive frame sync or left/right clock (LRCLK) (I/O/Z).
143 HR/W/AXR0[15]/AXR1[0] I
Host read or write select (I) [default] or McASP0 TX/RX pin 15 (I/O/Z) or McASP1 TX/RX pin 0 (I/O/Z).
Pin Function