66
1
2
4
1
2
4
C
D
F
A
B
E
TS7, BCT-1710, BCT-1720, BCT-1730
Note:
1
The following abbreviations are used: I - Input; O - Output; OD - Open drain output.
2
3.3 V output levels.
3
5 V tolerant
Pin Number
Name
I/O
1
Description
SIGNAL INPUTS
50, 51
IP, IN
I
Analog in Phase Component
53, 54
QN, QP
I
Analog in Quadrature Component
FRONT END CONTROLS
1
CLK_IN/XTAL IN
I
Crystal Input or CLK_IN
2
XTAL OUT
O
Crystal Output
9
AGC
OD
3
Control Signal to the Tuner
5
AUX_CLK
O
2
Programmable Output Port or Programmable Output Clock
17-18
OP0, OP1
O
2
Programmable Output Ports
19
LOCK/OP2
O
2
Carrier Found or Data Found or Output Port
38
IP0
I
Input Port
SIGNAL OUPUTS
26-28-29-31, 33 to 36
D[7:0]
O
2
Output Data; D7 is DATA_OUT in Serial Mode
24
CLK_OUT
O
2
Output Byte Clock; or Bit Clock in Serial Mode
22
STR_OUT
O
2
Output 1st byte Signal (synchro byte clock)
21
D/P
O
2
Data/Parity Signal
20
ERROR
O
2
Output Error Signal. Set in case of uncorrectible packet.
I
2
C INTERFACE
14
SCL
I
3
Serial Clock (I
2
C bus)
12
SDA
I/OD
3
Serial Data (I
2
C bus)
OTHERS
59
SCLT
OD
3
Tuner Serial Clock (repeator) or Output Port
60
SDAT
I/OD
3
Tuner Serial Data (repeator) or Input/Output Port
37-43-44-45-46-61-62
TEST
I
Reserved for manufacturing tests; must be tied to V
SS
58
DIRCLK_DIS
I
Sets the DIRCLK function at power on
3, 49, 52, 57
V
SSA
S
Analog Ground
V
DDA
S
Analog 2.5 V Supply
V
TOP
S
ADC High Voltage Reference
V
BOT
S
ADC Low Voltage Reference
V
SS
S
Ground
V
DD_3.3 V
S
3.3 V Supply
V
DD
S
2.5 V Supply
RESET
I
Reset, active at low level
STDBY
I
Sets STDBY at power on
16
F22/DiSEqC
O
2
DiSEqC modulation, 22 kHz Tone, Programmable
Output Port
40
DAC
O
2
Programmable Digital to Analog Converter Output
¶
Pin Function
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