Block Diagram and Testpoint Overview Bare Board
31
SD-5.31SL
6.
6.
Block Diagram and Testpoint Overview Bare Board
Block Diagram
Flash / ROM
2M Bytes
TSOP48
ATAPI connector
RESET 1 2 GND
DD7 3 4 DD8
ZK5 E-LINK connector
DD6 5 6 DD9
ATAPI connector
GND 1 2 +5V
UPA[1:22]
DD5 7 8 DD10
MEDUSACSn 3 4 +5V
UPD[0:15]
DD4 9 10 DD11
ZK5 E-LINK
ALE 5 6 SYSRSTn
SYSRSTn
DD3 11 12 DD12
connector
UPA2 7 8 UPA3
UDS
DD2 13 14 DD13
UPA15 9 10 UPA1
FLASHCSn
DD1 15 16 DD14
UPA13 11 12 UPD14
DD0 17 18 DD15
UPA[1:3]
UPA11 13 14 UPD12
GND 19 20 NC
UPD[0:15]
UPA[1:3]
UPA9 15 16 UPD10
DMARQ 21 22 GND
HDMARQ
UPD[0:15]
UPD8 17 18 GND
Transparent latch
DIOWn 23 24 GND
LDS
ALE
UPD6 19 20 UPD7
74HCT573
DIORn 25 26 GND
UDS
SYSRSTn
UPD4 21 22 UPD5
74HCT573
IORDYn 27 28 NC
HDTACKn
HDTACKn
UPD2 23 24 UPD3
74HCT573
DMACK 29 30 GND
HDMACK
MEDUSAINTn
UPD0 25 26 UPD1
INTRQ 31 32 NC
ATAPIINTn
UDS
MEDUSAINTn 27 28 DTACKn
DA1 33 34 NC
IDECS0n
LDS
LDS 29 30 UDS
DA0 35 36 DA2
IDECS1n
RWn
RWn 31 32 GND
UPA[1:3]
CS0n 37 38 CS1n
ATAPIRSTn
MEDUSACSn
UPD[0:15]
NC 39 40 GND
ALE
Two SDRAM configuration option
MA[0:11]
2x TSOP54 SDRAM
BA[0:1]
Host interface
ATAPI
2pcs x 1M x 16 x 4 = 128Mbits
MD[0:31]
MCS0n
MRASn
Clock
MCASn
SDRAM interface
circuit
MWEn
MCLK
MDQM[0:3]
MCS1n
SYSRSTn
Reset
circuit
I2S
KOK
A-D
Audio I2S output
Microphone
Digital
GPIO
I2C
I2C
Analog
Digital
XCLK
Service and
JTAG bus
Digital
Input
audio
SPDIF - I2S
(misc)
Master
Slave
video
audio
BCLK
diagnostic port
TRST
video
SPDIF
conv.
GPIO
MSCL
SCL
VDAC[0:4]
SPDIF
LRCLK
RTS1
TDO
VDATA(0:7)
Input
MSDA
SDA
ADATA[0:3]
RXD1
TDI
ITUT-656
I2C
TXD1
TMS
INT.
CTS1
TCK
Module interface bus
MSCL
MSDA
DAC
(2/6 Ch)
64kbits
NVRAM
Analog Audio Out
SD5.31 BLOCK DIAGRAM
OUTSW
INSW
HOMESW
Tray connector
Motor connector
1 LD-
1 SL-
2 LD+
Slot
Motor
2 SL+
3 OUTSW
connector
connector
3 GND
4 GND
4 HOMESW
5 INSW
5 H+
6 H-
7 H3-
H1+
8 H3+
H1-
A1
9 H2-
LD+
SL+
H2+
A2
10 H2+
LD-
SL-
H2-
A3
11 H1-
H3+
VH
12 H1+
H3-
13 A1
14 A2
15 A3
TR+
TR-
Servo driver
Spindle motor driver
FO+
BA5954FP
BA6849FP
FO-
OPU connector
1 TR-
MVREF2
2 TR+
MC34072
3 FO-
4 FO+
SFOCUS
SMOTOR
5 PDDVD
STRACK
SSPDON
6 VCC
TRAYSW
SFGIN
7 VR
RFRP
SSLEG
SB
8 GND
VC21
DRVSB
9 LDDVD
VC25
10 LDCD
VC21
PIN
11 VR
PI
12 GND
MEVO
13 PDCD
14 GND
Laser control
CEI
15 RFOUT
FEI
16 C
TEI
17 B
TEXI
MA[0:15]
A16
18 A
OPU
DVDLD
DVDLDO
SDFCT
MD[0:7]
19 D
connector
CDLD
CDLDO
SBAD
MFSCS
20 F
SEFGC
MPSEN
21 E
MIRR
MWR
22 VCC
SLDC
23 VS
SP-3721A
24 GND
DVDMDI
SCS
CDMDI
SDATA
SCLK
RA[0:11]
A
RD[0:15]
B
RRAS
EDO DRAM
KAS161622D
C
RFO
RCAS
256K x 16
D
RWE
SOJ40
E
ROE
F
RFOUT
UPA[1:3]
UPD[0:15]
HDMARQ
LDS
UDS
HDTACKn
HDMACK
ATAPIINTn
IDECS0n
IDECS1n
ATAPIRSTn
ATAPI connector
(for PCMCIA interface)
From Back-end Host
Flash / ROM
M29F002BT
Power-on
Reset
Front-End Engine
Front-End Engine
LSI Logic
Ziva5+
ALi
M5705
Clock
circuit
1M x 16 M29W160
Ext I2S Input
Audio I2S input
XCLK
BCLK
LRCLK
MUX
E-LINK
CL 36532043_043.eps
030603
Содержание SD-5.31SL
Страница 6: ...Directions for Use EN 6 SD 5 31SL 3 3 Directions for Use There is no DFU available ...
Страница 42: ...42 SD 5 31SL 7 Electrical Diagrams and PWB s Layout Bare Board Part 1 Top Side CL 36532043_32a eps 030603 ...
Страница 43: ...Electrical Diagrams and PWB s 43 SD 5 31SL 7 Layout Bare Board Part 2 Top Side CL 36532043_32b eps 030603 ...
Страница 45: ...Electrical Diagrams and PWB s 45 SD 5 31SL 7 Layout Bare Board Part 1 Bottom Side CL 36532043_33a eps 030603 ...
Страница 46: ...46 SD 5 31SL 7 Electrical Diagrams and PWB s Layout Bare Board Part 2 Bottom Side CL 36532043_33b eps 030603 ...
Страница 64: ...Revision List EN 64 SD 5 31SL 11 11 Revision List First release ...