Test Instructions Mono Board SD5.31SL
EN 11
SD-5.31SL
5.
5.
Test Instructions Mono Board SD5.31SL
5.1
General
•
Impedance of measuring-equipment should be > 1M
Ω
.
•
Most tests have to be done by software commands.
Together with the software command you will find a Ref.#
nbr. This is the number of the diagnostic nulceus used for
this test. More detailed information can be find in the
chapter “Diagnostic Nuclei”.
•
Levels: Most measurements are digital measurements.
The signal levels specification in this document are defined
in the chapter Technical Specifications.
•
All the waveforms measurement carried out in these test
instruction will be base on the testpoint indicated in the
Monoboard schematic diagram in the service manual.
5.2
General Start-up Measurements
5.2.1
Supply Check:
Table 5-1 Supply check
The monoboard operates in power-off and power-on mode
only. There is no standby mode. In power-off mode, the
monoboard does not respond to any communication or signals.
Reset is via an internal reset circuit, which are tied to the +3V3
supply. To ensure proper power recycling, the following timing
should be observed:
Figure 5-1 Timing chart
All tests that require the diagnostic software should be
performed in power-on mode only.
5.2.2
Reset Check:
To ensure a proper start-up of the monoboard, the back-end
reset signal SYS_RST is required at the ZIVA-5 input (testpoint
F501) after power-on.
To check the reset timing, measure the SYS_RST (testpoint
F501) and the +3V3ST supply (testpoint F503), reset circuit
trigger signal.
Figure 5-2 Reset
NB: The SYS_RST rising edge,CH2, should be at least
100msec after the +3V3ST (refer to CH1 Figure Reset).
If the reset input does not go high then check the reset circuit
around IC7500.
5.2.3
Clock Check
To check the correct functioning of the ZIVA, we first have to
check the presence of all clocks.
Table 5-2 Clock check
Figure 5-3 DA_XCK
No
Testland
Signal Name
DC Voltage (V)
Min
Typ
Max
1
F810
+3V3
3.15V
3.30V
3.50V
2
F811
+5V
4.75V
5.00V
5.25V
3
F813
+12V
10.0V
12.0V
13.2V
+12V
+12V
0V
+12VSTBY
+12V
0V
+3.3V
+3.3V
0V
+5V
+5V
0V
Internal
Reset
High
Low
3ms min
50ms min
Modes:-
Power-off
Reset mode
Operational mode
Standby mode
CL 36532043_044.eps
270503
No
Test
land
Signal
name
Frequency (MHz)
Descrip-
tion
Min
Typ
Max
1
F401
XTAL
13.4993 13.5000 13.5007
Back-end
clock
(± 50ppm)
2
F209 ALI_CLK 33.6994 33.8688 34.0382
Front-end
clock
(± 0.5%)
3
F421 DA_XCK 18.063
18.432
18.801
Audio
clock
4
F502 SD_CLK 119.070 121.500 123.930
SDRAM
clock
1
2
T
ch1
ch2
CH2 1.00V= MTB 500ms 4.96dv ch1+
CH1 1.00V=
PM3380B
CL 36532043_067.eps
030603
1
ch1
ch1 freq 18.5Mhz
CH1 1.00V= MTB 20.0ns ch1+
PM3380B
CL 36532043_057.eps
030603
Содержание SD-5.31SL
Страница 6: ...Directions for Use EN 6 SD 5 31SL 3 3 Directions for Use There is no DFU available ...
Страница 42: ...42 SD 5 31SL 7 Electrical Diagrams and PWB s Layout Bare Board Part 1 Top Side CL 36532043_32a eps 030603 ...
Страница 43: ...Electrical Diagrams and PWB s 43 SD 5 31SL 7 Layout Bare Board Part 2 Top Side CL 36532043_32b eps 030603 ...
Страница 45: ...Electrical Diagrams and PWB s 45 SD 5 31SL 7 Layout Bare Board Part 1 Bottom Side CL 36532043_33a eps 030603 ...
Страница 46: ...46 SD 5 31SL 7 Electrical Diagrams and PWB s Layout Bare Board Part 2 Bottom Side CL 36532043_33b eps 030603 ...
Страница 64: ...Revision List EN 64 SD 5 31SL 11 11 Revision List First release ...