Circuit Diagrams and PWB Layouts
8
5
7.
SSB: PNX5100: Debug
RE
S
ERVED
4
1
2
3
4
A
B
C
A
B
C
D
1CJ0 A
3
PNX5100: DEBUG
3
CJ0 C
3
3
CJ1 C
3
6CJ0 C
3
7CJ0 D
3
9CJ0 B
3
FCJ0 B
3
D
1
2
3
+
3
V
3
9CJ0
FCJ0
3
CJ0
33
0R
S
ML-
3
10
6CJ0
10K
3
CJ1
+
3
V
3
4
5
6
7
8
9
1
10
11
12
1
3
14
2
3
5-147279-
3
1CJ0
+
3
V
3
7CJ0
PDTC114EU
EJTAG-PNX5100-TR
S
Tn
EJTAG-PNX5100-TDI
EJTAG-PNX5100-TDO
EJTAG-PNX5100-TM
S
EJTAG-PNX5100-TCK
PNX5100-R
S
T-OUT
3
1
3
9 12
3
6214.4
I_17660_0
3
7.ep
s
110
3
0
8
B05H
B05H
Personal Notes:
E_06532_012.eps
131004