Circuit Descriptions and List of Abbreviations
9.
9.1.1
Input/Output
The main inputs are:
•
Basic: VGA only,
•
Enhanced: VGA, Flex-VGA, DVI-D, HD-RGB+HV, HD-
2fH-YPbPr (sync on Y), 1fH-YCbCr (sync on Y), YC, CVBS
on cinch. Flex-VGA gives the user a choice to configure the
'loop-through VGA output' as an output or as input.
9.1.2
Video
This mainly consists of an analogue processing part and a
digital processing part. The video inputs like VGA (Basic
configuration), CVBS, YC, HD-RGB/YUV (1fH and 2fH) and
DVI-D are received and processed.
The VGA signals are first converted to digital signals and then
processed by the PW Scaler.
The YPbPr (2fH) signal is discretely converted to RGB,
whereas the YCbCr (1fH) signal is processed in the SAA7118
Digital Video decoder.
The base-band video inputs (CVBS and YC) are output from
this decoder as digital YUV, which are then further processed
by the Pixel Works Scaler (PW).
The signals on the digital DVI input are first decoded by the
TMDS decoder inside the AD9887 and then processed by the
PW Scaler.
The PW Scaler output is going through an EPLD and then via
an LVDS Encoder to the SDI PDP (Plasma Display Panel) as
differential serial data. This PDP has a resolution of 852(H) x
480 (V) pixels.
9.1.3
Audio
This mainly hosts the audio inputs for the various video inputs.
They go through an I
2
C controlled source selector. The main
audio processing is done by the Micronas MSP3415G version
with built-in UltraBass-II algorithm.
A digital delay line is created using the I
2
S channel and SRAM.
The delay created can be selected between two values, one for
the Receiver box, and one for the Monitor.
The processed audio signals are then differentially transmitted
to the audio amplifier panel. This amplifier drives a tweeter and
a twin-drive woofer (low/mid range). Active filtering is done
prior to the amplifiers.
9.1.4
Control
The main controller is the OTC, referred to as the 'main
processor'. This operates in co-ordination with the processor in
the Pixel Works Scaler (PW), referred to as the 'co-processor'.
When the FM242 monitor is connected to an F21R Receiver
box, the UART commands from the Receiver box will control
the monitor.
In stand-alone mode, the monitor can be controlled via the
Remote Control or via the RS232C port.
DDC1/2B (Digital Data Channel, an I
2
C-based protocol) is
implemented with separate identification NVMs for the two
VGA inputs and the DVI-D input as well. In addition, the
RS232C port can be used for software download to the PW and
the OTC. The target for downloading is controlled via a switch
in the RS232C path; the switch itself is controlled by the OTC.
9.1.5
Power Supply
Figure 9-2 Power Supply Path
Audio processing
Audio amplifier
RC/LED/switch panel
3D Comb*
PW
PixelWorks
PW164_10R or 10RK
Video Scaling
Co-processor
OTC
Main Processor
SAA5801H/xx
LVDS
Encoder
DS90C385
Flash
ROM
2Mbyte
NVM
32Kbit
ADC +
TMDS
Decoder
AD9887
Y/G
Pb/B
Pr/R
H,V
Sync
decode
NVM
DDC
NVM
DDC
EPLD
EP1K30FC
PDP
Digital Video
Decoder
SAA7118
De-interlacer
SDA9400
MSP Audio Processor
MSP3415G
Audio Delay
32KSRAM CY7C1399
Flash ROM
2Mbyte
AC i/
p
CVBS
YC
Sub-D
9 P
DRAM
2Mbyte
SRAM
128kbyte
ADC Exp
PCF8591
IO Exp-
SC1
PCF8574
HP
Amp
LP
Amp
Tweeter
Low
VSND_NEG
VSND_POS
/Mid
Per channel
RS
232
C
V
G
A
2
ST
RS 232
Driver
NVM
32Kbit
PW/OTC
Switch
4052
! All Functional block s shaded grey are required for
the"Basic Configuration".
The remainder is required for the "Enhanced Configuration".
*
are optional or prepared
ON/OFF switch
(see description)
L/R CVBS
L/R VGA in
L/R DVI
L/R HD
L/R Flex VGA
(only output in
Basic config.)
Audio Switch
TEA6422D
L/R YC
Output
Switch
Video +
Sync
switching
PSU
AC/DC, DC/DC converters
Audio supply, 5V,8V6, 3v3, Vs,Va
Protection
3v3,5v Standby PSU
Fan driver
Vs,Va
VGA1
Switch
4052
Sync.
Interrupt
Gener.
MPU
PROM
for EPLD
Loop thru of RG
DVI-D
B
Flex
and H,V signals
from VGA1 only
UART
Interrupt
gener.
AV3
AV1
AV2
RC
out
YPbPr
RGB
Contro l
PSU
audio
enable
service
int. pins
RS232
Interrupt
gener.
Power ON
Reset
Clock
generator
+9V_STBY
+9V_STBY
+9V_STBY
IO expander
*
CL 26532038_007.eps
010502
+5V
+5V_STBY_SW
+5V
+5V
+8V6
+8V6
+8V6
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+5V
Connectors
+3V3_STBY_SW
+5V
Vpr2
Vcc
+2V5
+2V5
+8V6
+8V6
+8V6
+8V6
+5V
+8V6
+5V
VSND_NEG
VSND_POS
Video
Local
converter
D
V
I
+5V_STBY_SW
NVM
DDC
+5V_STB Y_SW
+9V_STBY_SW
+5V_STBY_SW
+5V
+5V_STBY_SW
+5V_STBY_SW
RC5 to RCout
buffer
RC5 to VGA1
buffer
+5V_STBY_SW
+5V_STBY_SW
+5V_STBY_SW
+8V6
+5V
+3V3_STBY_SW
+5V
+8V6
+5V_STBY_SW
+9V_STB Y
V
G
A
1
In
IR RXr
(RC in)
Light
Sensor
Red
LED
Green
LED
Discrete
electronics
Temp.Sensor
Mute
Mute
Содержание FM242
Страница 7: ...Directions for Use EN 7 FM242 AA 3 3 Directions for Use ...
Страница 8: ...Directions for Use EN 8 FM242 AA 3 ...
Страница 9: ...Directions for Use EN 9 FM242 AA 3 ...
Страница 31: ...Electrical Diagrams and PWB Layouts 31 FM242 AA 7 Audio Panel Supply Right High ...
Страница 66: ...66 FM242 AA 7 Electrical Diagrams and PWB Layouts Personal Notes Personal Notes ...
Страница 90: ...Revision List EN 90 FM242 AA 11 11 Revision List First release ...