EN 235
3139 785 31681
9.
Circuit- and IC description
Symbol
Pin
Number
Type
DESCRIPTION
T
4mA
demodulation, de-interleaving, RS decoding and de-scrambling.
In serial mode. This output can be set to tri-state (default state at reset).
S_OCLK
31
I/O
T
4mA
Serial Output CLock. S_OCLK is the output clock for the serial S_DO
output. S_OCLK is internally generated depending on which interface is
selected.
This output can be set to tri-state (default state at reset).
S_DEN
30
I/O
T
4mA
Serial Data Enable : this output signal is high when there is a valid data
on output bus S_DO.
This output can be set to tri-state (default state at reset).
S_PSYNC
28
I/O
T
4mA
Serial TS Pulse SYNChro. This output signal goes high when the sync
byte (47
16
) is provided, then it goes low until the next sync byte.
S_PSYNC is high during the first bit of the sync byte (47
16
) or during the 8
bit of the sync byte depending on I2C programming
This output can be set to tri-state (default state at reset).
S_UNCOR
27
I/O
T
4mA
Serial TS UNCORrectable packet. This output signal is high when the
provided packet is uncorrectable (during the 188 bytes of the packet).
The uncorrectable packet is not affected by the Reed Solomon decoder,
but the MSB of the byte following the sync byte is forced «1 » for the
MPEG2 process: Error Flag Indicator (if RSI and IEI are set low in the I2C
table).
This output can be set to tri-state (default state at reset).
SADDR[1:0]
10,11
I
(5v tol)
SADDR are the 2 LSBs of the I2C address of the TDA10046A.
The MSBs are internally set to 00010. Therefore the complete I2C
address of the TDA10046A is (MSB to LSB) : 0,0,0,0,1,0, SADDR[1],
SADDR[0].
SDA
8
I/O
(5v tol)
4mA
I2C data input. SDA is a bi-directional signal. It is the serial input/output of
the I2C internal block. A pull-up resistor (typically 4.7 k
Ω
) must be
connected between SDA and VDD for proper operation (Open Drain
output).
SCL
6
I
(5v tol)
I2C clock input. SCL should nominally be a square wave with a maximum
frequency of 400KHz. SCL is generated by the system I2C master.
TEST
12
I
(5v tol)
Test input pin. For normal operation of the TDA10046A, TEST must be
grounded.
ENSERI
13
I
(5v tol)
When high this pin enables the serial output transport stream through the
boundary scan pins (TRST,TDO,TCK,TDI,TMS).
Must be set low in boundary scan mode.
TRST
14
I/O
T
(5v tol)
4mA
Test ReSeT. This active low input signal is used to reset the TAP
controller when in boundary scan mode.
In normal mode of operation TRST must be set low.
In serial mode, TRST is the uncorrectable output (S_UNCOR)
TDO
20
O
T
(5v tol)
4mA
Test Data Out. This is the serial Test output pin used in boundary scan
mode. Serial Data are provided on the falling edge of TCK.
In Serial mode, TDO is the data output (S_DO).
TCK
18
I/O
T
(5v tol)
4mA
Test ClocK : an independent clock used to drive the TAP controller when
in boundary scan mode. In normal mode of operation, TCK must be set
low.
In serial mode, TCK is the clock output (S_OCLK).
TDI
17
I/O
T
Test Data In. The serial input for Test data and instruction when in
boundary scan mode. In normal mode of operation, TDI must be set to
Содержание DVDR9000H/10
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