EN 162
3139 785 31681
7.
Circuit Diagrams and PWB Layouts
Digital: 1394
DVDD
AVDD
NC
PLLGND
DGND
AGND
DECODER/
BIAS
DATA
INTERFACE
LINK
RECEIVED
CONTROL
STATE
MACHINE
LOGIC
TRANSMIT
CLOCK
PLL
XTAL OSC.
ENCODER
DATA
GENERATOR
CURRENT
AND
VOLTAGE
1
T
S
E
T
0
T
S
E
T
C|LKON
ISO_
LPS
CPS
PLLVDD
R0
R1
TPBIAS0
TPA0+
TESTM
TPA0-
TPB0+
TPB0-
XI
XO
TIMER
ARBITR’N
AND
PD
RESET_
CNA
PC2
PC1
PC0
D7
D6
D5
D4
D3
D2
D1
D0
CTL1
CTL0
LREQ
SYSCLK
TESTPIN
GND
VDD
D
E
V
R
E
S
E
R
B
C
D
E
F
G
H
I
1201 D1
1203 B1
2200 B2
2201 C2
2202 D1
2203 D2
2204 D2
2205 D2
2206 G3
2207 F2
2208 G3
2209 G2
2210 G2
not used
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
not used
9
10
11
12
13
14
A
B
C
D
E
F
G
H
I
A
BOARD_ID
2212 H1
2214 H2
2215 H2
2217 I2
2218 I2
2219 I2
2220 I2
2221 I3
2222 I3
2223 I3
2224 I4
2225 I4
2226 I4
2227 I4
2228 I5
2229 I5
2230 I5
2231 I6
2232 I6
2233 I6
2234 I6
2235 A5
2236 A9
2237 B6
3200 E6
3202 F12
3203 H5
3204 D6
3205 A2
3206 A7
3207 A8
3208 B7
3209 B8
3210 B12
3211 B12
3212 B2
3213 B3
3214 B12
d
e
s
u t
o
n
3215 C12
3216 B7
3217 C12
3218 C12
3219 C12
3220 B7
3221 C12
3222 C12
3223 B7
3224 C12
3225 B7
3226 C12
3227 C12
3228 C7
3229 C12
3230 C12
3231 C7
3232 C2
3233 C2
3234 C7
3235 C12
3236 C7
3237 D12
3238 C7
3239 D12
3240 C2
3241 D12
3242 C7
3243 D12
3244 D12
3245 C7
3246 D12
3247 D12
3248 D7
3249 D12
3250 E12
3251 D12
3252 E12
3253 D2
3254 E12
not used
NI
V
D
d
e
s
u t
o
n
PHY
not used
3255 E12
3256 E12
3257 E12
3258 E12
3259 E12
3260 F12
3261 E3
3262 F7
3263 F7
3264 F7
3265 F7
3266 F7
3267 F7
3268 F7
3269 G7
3270 F12
3271 F12
3272 F12
3273 G8
3274 F12
3275 G4
3276 G7
3277 F12
3278 F12
3279 F12
3280 A6
3281 A7
3282 A8
3283 A2
3284 A8
3285 A6
3286 H13
3287 H13
3288 H13
3289 H13
3290 I13
3291 I13
3292 I13
3293 I13
3294 F12
3295 F12
3296 F12
3297 E8
3298 F8
3299 F8
3314 F13
3315 F8
3316 F8
3317 F8
3318 F8
3319 F8
4201 D6
4202 D6
4203 G12
4204 G12
4205 A4
5200 F2
5201 F4
5202 G2
5203 H2
5204 I1
6200 G4
7200 A5
7201 B12
7202 H5
not used
LINK
F1201 B2
F1202 B2
F1203 B1
F1204 B2
F1205 B2
F200 C12
F201 C9
F203 C3
F204 C13
F205 C12
F206 C13
F207 C12
F208 C12
F209 C12
F210 C13
F211 B12
F212 B12
F213 B12
F214 C12
F215 C12
F216 C12
F217 C12
I200 H4
I201 F2
I202 G2
I203 H2
I204 I2
I205 G11
I206 G4
I207 A3
I208 A3
I209 B3
I210 C2
I211 B7
I212 B7
I213 D6
I214 D6
I215 A6
I216 B6
I217 A8
I218 C7
I219 C7
I220 F12
I221 F12
I222 C7
I223 F12
I224 G8
I225 C7
I226 C7
I227 C7
3264
4K7
10K
3283
I222
F216
4K7
3269
2
8
2
3
K
0
1
K
0
1
PDTC144EU
8
0
2
3
7202
9
2
2
2
n
0
0
1
3
0
2
2
I227
p
2
1
4
1
3
3
K
0
1
I217
5200
10R
3273
BLMP18P
F213
1
3
2
2
n
0
0
1
33R
3243
I213
I216
2
1
2
2
u
0
0
1
0
0
1
3
H
M
L
T
0
0
2
6
6
0
2
2
n
0
0
1
38
59
60
41
53
2
29
28
27
37
36
35
34
45
46
47
20
21
22
14
57
58
56
40
61
62
23
15
1
54
55
16
43
44
10
11
12
13
17
18
63
64
25
26
51
52
3
24
4
5
19
6
7
8
9
32
33
39
48
49
50
30
31
42
7200
PDI1394P25
PDI1394P25
0
1
2
2
n
0
0
1
F201
R
6
5
3
3
2
3
n
0
0
1
7
2
2
2
%
1
3230
10K
220R
3317
3221
33R
F206
3284
1R0
2205
100n
4
1
2
2
n
0
0
1
4202
1
9
2
3
7
K
4
220R
3274
10R
3220
3277
220R
220R
3296
3294
220R
33R
3251
7
K
4
9
8
2
3
3297
220R
K
0
1
6
0
2
3
F210
n
0
0
1
5
2
2
2
33R
3214
6
3
2
2
n
0
0
1
33R
3229
3272
220R
0
4
2
3
10K
3235
%
1
1
K
5
3268
4K7
220R
3318
BLMP18P
5204
7
0
2
2
n
0
0
1
3242
10R
3244
33R
3227
33R
2204
100n
F208
7
K
4
7
8
2
3
2235
1n0
I211
3223
10R
p
0
7
2
1
0
2
2
%
1
R
6
5
2
3
2
3
3205
6K34
I224
1%
I208
33R
3222
n
0
0
1
0
3
2
2
0
9
2
3
7
K
4
I219
F1201
n
0
0
1
0
2
2
2
I215
9
1
2
2
n
0
0
1
3253
1R0
3
3
2
2
n
0
0
1
n
0
0
1
2
3
2
2
22K
3257
10R
3236
F1205
%
1
R
6
5
2
1
2
3
3255
4K7
82R
3224
4K7
3265
3248
22R
I221
I212
I207
n
0
0
1
3266
4K7
2
2
2
2
1
2
2
2
n
0
0
1
n
0
0
1
R
0
3
3
5
7
2
3
4
3
2
2
3316
220R
F1203
3210
33R
4204
I205
5202
1
8
2
3
K
0
1
BLMP18P
7
K
4
2
9
2
3
3238
10R
I218
F1202
F1204
220R
3279
10R
3228
3315
220R
I203
7
1
2
2
n
0
0
1
10R
3231
1R0
3209
8
0
2
2
V
5
3
7
u
4
33R
3247
4K7
3263
5
0
2
4
3319
220R
33R
3246
10K
3219
33R
3211
33R
3217
33R
3226
220R
3298
4K7
3267
3245
10R
I204
6
0
2I
I225
4K7
3256
1
0
2
5
3215
33R
3216
10R
0
1
2I
3218
33R
n
0
0
1
3
2
2
2
R
0
1
5
8
2
3
n
0
0
1
9
0
2
2
33R
3237
3270
220R
3252
33R
0
8
2
3
K
0
1
7
K
4
6
8
2
3
0
0
2
3
K
0
1
F217
I214
3276
1K0
220R
3202
K
0
1
3
0
2
3
3249
33R
6
2
2
2
n
0
0
1
n
0
0
1
7
3
2
2
3295
220R
3225
10R
5203
BLMP18P
3241
33R
4203
3239
33R
8
2
2
2
n
0
0
1
F214
3259
4K7
220R
3260
10K
3204
0
0
2I
K
0
1
7
0
2
3
F200
220R
3278
F211
3262
4K7
4K7
3250
3
9
2
3
7
K
4
n
0
0
1
8
1
2
2
3258
22K
n
0
0
1
1394
5
1
2
2
0
7
10R
3234
3
1
1
0
2
1
2
3
1
8
3
1
2
1
8
1
4
2
5
3
4
4
4
5
1
6
SCLK
62
1
63
2
64
3
6
8
7
4
8
0
9
5
9
7
0
1
3
52
4
58
5
59
6
72
7
71
8
104
9
42
RESET_
88
67
12
68
13
105
14
129
15
144
16
130
17
50
2
51
79
PHYD3
76
PHYD4
75
PHYD5
74
PHYD6
73
PHYD7
49
1
65
10
66
11
91
LPS
87
LREQ
LREQ
48
PD
86
PHYCTL0
85
PHYCTL1
82
PHYD0
81
PHYD1
80
PHYD2
38
HIFINT_
46
HIFMUX
HIFRD_
40
HIFSC_
36
41
HIFWAIT
HIFWR_
37
93
ISON
92
LINKON
HIFALE
8
HIFD10
7
HIFD11
4
HIFD12
3
HIFD13
2
HIFD14
1
HIFD15
10
HIFD8
9
HIFD9
21
HIFAD1
20
HIFAD2
19
HIFAD3
16
HIFAD4
15
HIFAD5
14
HIFAD6
13
HIFAD7
39
31
HIFA2
30
HIFA3
29
HIFA4
28
HIFA5
27
HIFA6
26
HIFA7
25
HIFA8
22
HIFAD0
7
1
3
2
4
3
3
4
3
5
0
6
9
6
45
HIF16BIT
33
HIFA0
32
HIFA1
7
7
3
8
9
8
4
9
6
0
1
2
1
1
9
1
1
1
3
1
7
3
1
1
1
125
AV2FSYNC
143
AV2READY
126
AV2SY
128
AV2SYNC
127
AV2VALID
55
CLK50
56
CYCLEIN
57
CYCLEOUT
5
136
AV2D3
139
AV2D4
140
AV2D5
141
AV2D6
142
AV2D7
123
AV2ENDPCK
121
AV2ERR0|LTLEND
AV2ERR1|DATINV
122
118
AV1READY
101
AV1SY
103
AV1SYNC
102
AV1VALID
124
AV2CLK
133
AV2D0
134
AV2D1
135
AV2D2
114
AV1D4
115
AV1D5
116
AV1D6
117
AV1D7
98
AV1ENDPCK
96
AV1ERR0
97
AV1ERR1
100
AV1FSYNC
47
1394MODE
99
AV1CLK
108
AV1D0
109
AV1D1
110
AV1D2
111
AV1D3
1
V
A
R
E
VI
E
C
E
R /
R
E
T
TI
M
S
N
A
R
T
2
V
A
R
E
VI
E
C
E
R /
R
E
T
TI
M
S
N
A
R
T
ISOCH & ASYNC
INTERFACE
12KB BUFFER
PACKETS
MEMORY
TRANSMITTER
8-BIT
RECEIVER
ASYNC
AND
REGISTERS
CONTROL
STATUS
AND
CORE
LINK
PDI1394L40
7201
I223
3254
I209
33R
F207
F204
4
2
2
2
n
0
0
1
F209
I201
24M576
1201
CX-8045G
8
8
2
3
7
K
4
F205
F215
F203
I220
I202
R
6
5
3
1
2
3
1203
1
2
3
4
5
6
%
1
SR
220R
3299
220R
3271
F212
I226
0
R
1
1
6
2
3
p
2
1
2
0
2
2
4201
+3V3_LINK
XIO_SEL1
MX_D_CTL
2200
1u0
PCI_AD(3)
PCI_AD(2)
PCI_AD(1)
PCI_AD(0)
L_CLK
L_VAL
L_SYNC
L_FSYNC
PCI_AD(31:0)
PCI_AD(8)
PCI_AD(7)
PCI_AD(6)
PCI_AD(5)
PCI_AD(4)
+3V3_IEEE_A
PCI_AD(31:0)
PCI_AD(31)
PCI_AD(30)
PCI_AD(29)
PCI_AD(28)
PCI_AD(27)
PCI_AD(26)
PCI_AD(25)
PCI_AD(24)
n
4
9
3
1
_
T
E
S
E
R
+3V3_IEEE_PLL
N
W
O
D
R
E
W
O
P
_
4
9
3
1
_
1
2
OI
P
M
+3V3_IEEE_D
+3V3_IEEE_D
L_D_CTL
MPIO9_BOARD_ID_0
MPIO10_BOARD_ID_1
MPIO11_HDMI_RESETn
MPIO12_HDMI_IRQ
+3V3_IEEE_D
MPIO8_1394_CNA
+3V3_LINK
+3V3_IEEE_D
+3V3_IEEE_D
+3V3_IEEE_PLL
+3V3_IEEE_A
+3V3
L_D(2)
MX_D(6)
MX_D(7)
MX_D(7:0)
MX_VAL
MX_SYNC
MX_CLK
+3V3_LINK
AV1ENDPCK
MPIO23_1394_LED
+5V
+3V3_LINK
MPIO2_1394_IRQn
MX_D(0)
MX_D(1)
MX_D(2)
MX_D(3)
MX_D(4)
MX_D(5)
L_D(7:0)
L_D(7)
L_D(6)
L_D(5)
L_D(4)
L_D(3)
L_D(1)
L_D(0)
+3V3_LINK
+3V3_IEEE_D
+3V3_IEEE_D
+3V3_LINK
+3V3_LINK
+3V3
+3V3
+3V3_LINK
+3V3_LINK
+3V3_LINK
PCI_CBE(1)
PCI_CBE(2)
3103_603_30601_a2_sh130_sh2.pdf 2004-12-01
Содержание DVDR9000H/10
Страница 135: ...EN 135 3139 785 31681 6 Block Diagrams Waveforms Wiring Diagram Waveforms of HDMI Board F111 P H_SYNC F112 P V_SYNC ...
Страница 186: ...EN 186 3139 785 31681 7 Circuit Diagrams and PWB Layouts DTTM Top Component View 123_4406_132_1 pdf 2004 04 28 ...
Страница 187: ...EN 187 3139 785 31681 DTTM Bottom Component View 7 Circuit Diagrams and PWB Layouts 123_4406_132_2 pdf 2004 04 28 ...
Страница 188: ...EN 188 3139 785 31681 7 Circuit Diagrams and PWB Layouts Notes ...
Страница 205: ...EN 205 3139 785 31681 9 Circuit and IC description IC7203 NJM2267M Dual Video 6dB Amplifier BLOCK DIAGRAM Figure 9 14 ...
Страница 209: ...EN 209 3139 785 31681 9 Circuit and IC description IC TMP87PM74ZFG Microprocessor PIN CONFIGURATION Figure 9 18 ...