Trouble Shooting
GB 14
CDR Mozart
5.
Reset & Clock Check
Switch on the
Power Supply
Power On Reset (+3V3) testpoint R1
OK
OK
OK
OK
OK
OK
OK
OK
NOK
Check IC7000
NOK
Check IC7000
Check IC7000
NOK
RST ADDA (+3V3) testpoint R2
RST FREYA (+3V3) testpoint R3
RESET Signals
OK
CLOCK Signals
OK
MAIN_CLK 33,8688MHz testpoint R4
NOK
Check X-tal 1005
Check D6002 and D6003
Check IC7000
NOK
Check IC7000
NOK
Check IC7004
SYS_CLK 16,9MHz testpoint R5
FREYA_CLK 8,5MHz testpoint R6
Check IC7012
Check R3019
NOK
Check IC7010
Check R3028
DAC_CLK 16,9MHz testpoint R7
ADC_CLK 16,9MHz testpoint R8
IO_CLK 16,9MHz testpoint R9
IO_CLK ABBA testpoint R10
RESET & CLOCK CHECK
USE MOZART MAIN BOARD CIRCUIT DIAGRAM 1 AND MOZART MAIN BOARD BOTTOM-AND TOP VIEW: TESTPOINTS
ch1
ch1: pkpk= 4.50 V
ch1: freq= 33.8MHz
CH1 1.00 V~ MTB20.0ns ch1+
1
ch1
ch1: pkpk= 3.34 V
ch1: freq= 16.9MHz
CH1 1.00 V~ MTB20.0ns ch1+
1
ch1
ch1: pkpk= 4.12 V
ch1: freq= 8.51MHz
CH1 1.00 V~ MTB50.0ns ch1+
1
ch1
ch1: pkpk= 3.50 V
ch1: freq= 16.9MHz
CH1 1.00 V~ MTB20.0ns ch1+
1
R4
R5
R6
R7
R8
R9
R10
Display uP generates
the Power On Reset
Check connection to Display board
CL 16532046_007.eps
101001