Circuit Description
GB 95
A10PTV2.0 NTSC
9.
Voltage module, shutting it Off. The CRT_PROT line will also
go low, shutting the RGB amplifiers to the CRT panels off.
In the case of Overcurrent, the voltage on Pin 3 of the High
Voltage module will drop, turning transistor 7909 on, turning
7908 on, latching 7907 and 7908. This will remove the 7.5-
volt turn on voltage at Pin 8 of the High Voltage module,
turning it off. During turn on, transistor 7906 is biased off
while capacitor 2913 charges. This prevents the shutdown
latch from turning on while the High Voltage module is turning
on.
9.8
Digital Convergence Circuit
CRT’s and Yokes are not linear devices. (Figure 28)
Therefore, a convergence circuit is necessary to align the
beams of all three tubes over the entire screen. The
Convergence panel is powered by a +32 volt, a -32 and a +15
volt supply from the Power Supply panel. A Line Sync (H
PUL) and a Frame Sync (V PUL) from the Scan High Voltage
panel keeps the Convergence Correction waveforms
synchronized to the deflection system. The SDA and SCL
lines on Pins 32 and 34 allow the microprocessor on the SSM
Panel to communicate with the microprocessor on the SSB
Panel. During the Convergence alignment mode, the
crosshatch pattern is generated in the Convergence circuit.
Red, Blue, Green, and Fast Blanking are fed to the Interface
panel and then to the Small Signal panel to be inserted into
the video drive.
There are two plus 5-volt regulators, and a -5 volt regulator in
the convergence circuit. (Figure 29) These are fed by the
plus 15 volt SSB, and the -32 volt supplies from the Large
Signal Panel. The 5-volt supply feeds the microprocessor
while the 5VA supply feeds the Digital to Analog converter
IC’s. The Plus and minus 32 volt supplies provide power to
the output IC's 7012 and 7014.
The Convergence panel has a phase-locked loop oscillator,
which produces a 13.59 MHz signal. (Figure 30) This signal
is phase locked to the 15650 Hz PAL or the 15734 Hz NTSC
Line Blanking pulse (HPUL). This signal is used as the
system clock, which is used by the convergence spline
processor (CSP), and the three digital to analog converters
(DACS). Therefore, the convergence correction waveforms
are synchronized to the deflection system of the television
set. Operational amplifier 7001 is used as an inverting two
pole Sallen_Key filter, which acts as the loop filter. Transistor
7000 and 7001 make up the oscillator.
When the set is turned on, the microprocessor on the Small
Signal panel reads the data stored in 7007 on the
Convergence panel via the I2C bus. This information
contains the x-y coordinates for the 35 alignment points of
each color visible on the screen during convergence set up
along with other register settings used by the csp.
The csp uses fourth order polynomial equations called
quadric splines in the algorithm to convert the data of the 35
(7 horizontal by 5 vertical) alignment points into 24 points per
horizontal 486 vertical lines for NTSC. When using PAL or
SECAM, the algorithm converts the data of the 35 (7
horizontal by 5 vertical) alignment points into 24 points per
horizontal line by 666 vertical lines. The resulting digital data
is supplied to 7009, 7011 and 7010; the three two channel
dacs, which convert the digital data into analog convergence
correction signals for red, green, and blue horizontal and
vertical. The csp outputs are approximately 1 to 2 volts peak
to peak with a 2.5-volt dc offset. The csp also supplies a 375
KHz 5-volt peak to peak ws or word select signal to select the
proper channel on the dac for horizontal (Line) or vertical
(Frame).
The Convergence correction waveforms may be disabled for
set up procedures by shorting connector 1005.
The output of the dac’s are amplified and filtered by IC200,
IC201, and IC202 before being fed to the Yoke drive
amplifiers.
If for some reason the set needs to be converged in the field,
the csp generates a cross hatch pattern with an intensified
cross. Control for 7003 csp is done by the microprocessor on
the SSB Panel. The R, G, G, Fast Blanking, and Intensity
signals used to display the pattern are output on Pins 29, 30,
31, 25, and 26 on 7003.
